drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
Extension
.c
Size
20472 bytes
Lines
736
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (quirks) {
			eeprom_cfg->max_i2c_read_len = quirks->max_read_len;
			eeprom_cfg->max_i2c_write_len = quirks->max_write_len;
		}
	}

	/*
	 * amdgpu_bad_page_threshold is used to config
	 * the threshold for the number of bad pages.
	 * -1:  Threshold is set to default value
	 *      Driver will issue a warning message when threshold is reached
	 *      and continue runtime services.
	 * 0:   Disable bad page retirement
	 *      Driver will not retire bad pages
	 *      which is intended for debugging purpose.
	 * -2:  Threshold is determined by a formula
	 *      that assumes 1 bad page per 100M of local memory.
	 *      Driver will continue runtime services when threhold is reached.
	 * 0 < threshold < max number of bad page records in EEPROM,
	 *      A user-defined threshold is set
	 *      Driver will halt runtime services when this custom threshold is reached.
	 */
	if (amdgpu_bad_page_threshold == NONSTOP_OVER_THRESHOLD)
		eeprom_cfg->eeprom_record_threshold_count =
			div64_u64(adev->gmc.mc_vram_size, TYPICAL_ECC_BAD_PAGE_RATE);
	else if (amdgpu_bad_page_threshold == WARN_NONSTOP_OVER_THRESHOLD)
		eeprom_cfg->eeprom_record_threshold_count =
				COUNT_BAD_PAGE_THRESHOLD(RAS_RESERVED_VRAM_SIZE_DEFAULT);
	else
		eeprom_cfg->eeprom_record_threshold_count = amdgpu_bad_page_threshold;

	eeprom_cfg->eeprom_record_threshold_config = amdgpu_bad_page_threshold;

	return 0;
}

static int amdgpu_ras_mgr_init_mp1_config(struct amdgpu_device *adev,
		struct ras_core_config *config)
{
	struct ras_mp1_config *mp1_cfg = &config->mp1_cfg;
	int ret = 0;

	switch (config->mp1_ip_version) {
	case IP_VERSION(13, 0, 6):
	case IP_VERSION(13, 0, 14):
	case IP_VERSION(13, 0, 12):
		mp1_cfg->mp1_sys_fn = &amdgpu_ras_mp1_sys_func_v13_0;
		break;
	default:
		RAS_DEV_ERR(adev,
			"The mp1(0x%x) ras config is not right!\n",
			config->mp1_ip_version);
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int amdgpu_ras_mgr_init_nbio_config(struct amdgpu_device *adev,
		struct ras_core_config *config)
{
	struct ras_nbio_config *nbio_cfg = &config->nbio_cfg;
	int ret = 0;

	switch (config->nbio_ip_version) {
	case IP_VERSION(7, 9, 0):
	case IP_VERSION(7, 9, 1):
		nbio_cfg->nbio_sys_fn = &amdgpu_ras_nbio_sys_func_v7_9;
		break;
	default:
		RAS_DEV_ERR(adev,
			"The nbio(0x%x) ras config is not right!\n",
			config->nbio_ip_version);
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int amdgpu_ras_mgr_get_ras_psp_system_status(struct ras_core_context *ras_core,
			struct ras_psp_sys_status *status)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
	struct ta_context *context = &adev->psp.ras_context.context;

	status->initialized = context->initialized;
	status->session_id = context->session_id;
	status->psp_cmd_mutex = &adev->psp.mutex;

Annotation

Implementation Notes