drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h
Extension
.h
Size
3486 bytes
Lines
88
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ras_ih_info {
	uint32_t block;
	union {
		struct amdgpu_iv_entry iv_entry;
		struct {
			uint16_t pasid;
			uint32_t reset;
			pasid_notify pasid_fn;
			void *data;
		};
	};
};

struct amdgpu_ras_mgr {
	struct amdgpu_device *adev;
	struct ras_core_context *ras_core;
	struct delayed_work retire_page_dwork;
	struct ras_event_manager ras_event_mgr;
	void *virt_ras_cmd;
	uint64_t last_poison_consumption_seqno;
	bool ras_is_ready;

	bool is_paused;
	struct completion ras_event_done;
};

extern const struct amdgpu_ip_block_version ras_v1_0_ip_block;

struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(
			struct amdgpu_device *adev);
int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable);
bool amdgpu_uniras_enabled(struct amdgpu_device *adev);
int amdgpu_ras_mgr_handle_fatal_interrupt(struct amdgpu_device *adev, void *data);
int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void *data);
int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data);
int amdgpu_ras_mgr_dispatch_interrupt(struct amdgpu_device *adev, struct ras_ih_info *ih_info);
int amdgpu_ras_mgr_update_ras_ecc(struct amdgpu_device *adev);
int amdgpu_ras_mgr_reset_gpu(struct amdgpu_device *adev, uint32_t flags);
uint64_t amdgpu_ras_mgr_gen_ras_event_seqno(struct amdgpu_device *adev,
			enum ras_seqno_type seqno_type);
bool amdgpu_ras_mgr_check_eeprom_safety_watermark(struct amdgpu_device *adev);
int amdgpu_ras_mgr_get_curr_nps_mode(struct amdgpu_device *adev, uint32_t *nps_mode);
bool amdgpu_ras_mgr_check_retired_addr(struct amdgpu_device *adev,
			uint64_t addr);
bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev);
int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev,
		uint32_t cmd_id, void *input, uint32_t input_size,
		void *output, uint32_t out_size);
int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev);
int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev);
int amdgpu_ras_mgr_lookup_bad_pages_in_a_row(struct amdgpu_device *adev,
		uint64_t addr, uint64_t *nps_page_addr, uint32_t max_page_count);
#endif

Annotation

Implementation Notes