drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c- Extension
.c- Size
- 4545 bytes
- Lines
- 141
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu_smu.hamdgpu_reset.hamdgpu_ras_mp1_v13_0.h
Detected Declarations
function mp1_v13_0_get_valid_bank_countfunction mp1_v13_0_dump_valid_bankfunction mp1_v13_0_eeprom_send_msgfunction mp1_v13_0_get_ras_enabled_mask
Annotated Snippet
if (ret) {
RAS_DEV_ERR(adev, "ACA failed to read register[%d], offset:0x%x\n",
reg_idx, offset);
break;
}
}
up_read(&adev->reset_domain->sem);
if (!ret)
*val = (uint64_t)data[1] << 32 | data[0];
} else {
ret = -RAS_CORE_GPU_IN_MODE1_RESET;
}
return ret;
}
static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core,
enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg)
{
struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
int ret = 0;
if (down_read_trylock(&adev->reset_domain->sem)) {
ret = amdgpu_smu_ras_send_msg(adev,
pmfw_eeprom_msgs[index], param, read_arg);
up_read(&adev->reset_domain->sem);
} else {
ret = -RAS_CORE_GPU_IN_MODE1_RESET;
}
return ret;
}
static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core,
uint64_t *enabled_mask)
{
struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
int ret = 0;
if (down_read_trylock(&adev->reset_domain->sem)) {
if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT))
*enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM;
up_read(&adev->reset_domain->sem);
} else {
ret = -RAS_CORE_GPU_IN_MODE1_RESET;
}
return ret;
}
const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = {
.mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count,
.mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank,
.mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg,
.mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask,
};
Annotation
- Immediate include surface: `amdgpu_smu.h`, `amdgpu_reset.h`, `amdgpu_ras_mp1_v13_0.h`.
- Detected declarations: `function mp1_v13_0_get_valid_bank_count`, `function mp1_v13_0_dump_valid_bank`, `function mp1_v13_0_eeprom_send_msg`, `function mp1_v13_0_get_ras_enabled_mask`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.