drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c- Extension
.c- Size
- 4493 bytes
- Lines
- 126
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu_ras_mgr.hamdgpu_ras_nbio_v7_9.hnbio/nbio_7_9_0_offset.hnbio/nbio_7_9_0_sh_mask.hivsrcid/nbio/irqsrcs_nbif_7_4.h
Detected Declarations
function filesfunction nbio_v7_9_process_ras_controller_irqfunction nbio_v7_9_set_ras_err_event_athub_irq_statefunction nbio_v7_9_process_err_event_athub_irqfunction nbio_v7_9_init_ras_controller_interruptfunction nbio_v7_9_init_ras_err_event_athub_interrupt
Annotated Snippet
// SPDX-License-Identifier: MIT
/*
* Copyright 2025 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "amdgpu_ras_mgr.h"
#include "amdgpu_ras_nbio_v7_9.h"
#include "nbio/nbio_7_9_0_offset.h"
#include "nbio/nbio_7_9_0_sh_mask.h"
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned int type,
enum amdgpu_interrupt_state state)
{
/* Dummy function, there is no initialization operation in driver */
return 0;
}
static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
/* By design, the ih cookie for ras_controller_irq should be written
* to BIFring instead of general iv ring. However, due to known bif ring
* hw bug, it has to be disabled. There is no chance the process function
* will be involked. Just left it as a dummy one.
*/
return 0;
}
static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned int type,
enum amdgpu_interrupt_state state)
{
/* Dummy function, there is no initialization operation in driver */
return 0;
}
static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
/* By design, the ih cookie for err_event_athub_irq should be written
* to BIFring instead of general iv ring. However, due to known bif ring
* hw bug, it has to be disabled. There is no chance the process function
* will be involked. Just left it as a dummy one.
*/
return 0;
}
static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = {
.set = nbio_v7_9_set_ras_controller_irq_state,
.process = nbio_v7_9_process_ras_controller_irq,
};
static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = {
.set = nbio_v7_9_set_ras_err_event_athub_irq_state,
.process = nbio_v7_9_process_err_event_athub_irq,
};
static int nbio_v7_9_init_ras_controller_interrupt(struct ras_core_context *ras_core, bool state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
int r;
/* init the irq funcs */
Annotation
- Immediate include surface: `amdgpu_ras_mgr.h`, `amdgpu_ras_nbio_v7_9.h`, `nbio/nbio_7_9_0_offset.h`, `nbio/nbio_7_9_0_sh_mask.h`, `ivsrcid/nbio/irqsrcs_nbif_7_4.h`.
- Detected declarations: `function files`, `function nbio_v7_9_process_ras_controller_irq`, `function nbio_v7_9_set_ras_err_event_athub_irq_state`, `function nbio_v7_9_process_err_event_athub_irq`, `function nbio_v7_9_init_ras_controller_interrupt`, `function nbio_v7_9_init_ras_err_event_athub_interrupt`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.