drivers/gpu/drm/amd/ras/rascore/ras_cper.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras_cper.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/rascore/ras_cper.c
Extension
.c
Size
10374 bytes
Lines
316
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright 2025 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "ras.h"
#include "ras_core_status.h"
#include "ras_log_ring.h"
#include "ras_cper.h"

static const struct ras_cper_guid MCE	= CPER_NOTIFY__MCE;
static const struct ras_cper_guid CMC	= CPER_NOTIFY__CMC;
static const struct ras_cper_guid BOOT	= BOOT__TYPE;

static const struct ras_cper_guid CRASHDUMP = GPU__CRASHDUMP;
static const struct ras_cper_guid RUNTIME = GPU__NONSTANDARD_ERROR;

static void cper_get_timestamp(struct ras_core_context *ras_core,
		struct ras_cper_timestamp *timestamp, uint64_t utc_second_timestamp)
{
	struct ras_time tm = {0};

	ras_core_convert_timestamp_to_time(ras_core, utc_second_timestamp, &tm);
	timestamp->seconds = tm.tm_sec;
	timestamp->minutes = tm.tm_min;
	timestamp->hours = tm.tm_hour;
	timestamp->flag = 0;
	timestamp->day = tm.tm_mday;
	timestamp->month = tm.tm_mon;
	timestamp->year = tm.tm_year % 100;
	timestamp->century = tm.tm_year / 100;
}

static void fill_section_hdr(struct ras_core_context *ras_core,
				struct cper_section_hdr *hdr, enum ras_cper_type type,
				enum ras_cper_severity sev, struct ras_log_info *trace)
{
	struct device_system_info dev_info = {0};
	char record_id[32];

	hdr->signature[0]		= 'C';
	hdr->signature[1]		= 'P';
	hdr->signature[2]		= 'E';
	hdr->signature[3]		= 'R';
	hdr->revision			= CPER_HDR__REV_1;
	hdr->signature_end		= 0xFFFFFFFF;
	hdr->error_severity		= (sev == RAS_CPER_SEV_RMA ? RAS_CPER_SEV_FATAL_UE : sev);

	hdr->valid_bits.platform_id	= 1;
	hdr->valid_bits.timestamp	= 1;

	ras_core_get_device_system_info(ras_core, &dev_info);

	cper_get_timestamp(ras_core, &hdr->timestamp, trace->timestamp);

	snprintf(record_id, sizeof(record_id), "%d:%llX", dev_info.socket_id,
		    RAS_LOG_SEQNO_TO_BATCH_IDX(trace->seqno));
	memcpy(hdr->record_id, record_id, 8);

	snprintf(hdr->platform_id, 16, "0x%04X:0x%04X",
		dev_info.vendor_id, dev_info.device_id);
	/* pmfw version should be part of creator_id according to CPER spec */
	snprintf(hdr->creator_id, 16, "%s", CPER_CREATOR_ID__AMDGPU);

	switch (type) {
	case RAS_CPER_TYPE_BOOT:
		hdr->notify_type = BOOT;
		break;
	case RAS_CPER_TYPE_FATAL:
	case RAS_CPER_TYPE_RMA:
		hdr->notify_type = MCE;
		break;

Annotation

Implementation Notes