drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
Extension
.h
Size
3557 bytes
Lines
88
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ras_fw_eeprom_control {
	uint32_t version;
	/* record threshold */
	int record_threshold_config;
	uint32_t record_threshold_count;
	bool update_channel_flag;

	/* Number of records in the table.
	 */
	u32 ras_num_recs;

	/* Maximum possible number of records
	 * we could store, i.e. the maximum capacity
	 * of the table.
	 */
	u32 ras_max_record_count;

	/* Protect table access via this mutex.
	 */
	struct mutex ras_tbl_mutex;

	/* Record channel info which occurred bad pages
	 */
	u32 bad_channel_bitmap;
};

void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
int ras_fw_get_table_version(struct ras_core_context *ras_core,
				     uint32_t *table_version);
int ras_fw_get_badpage_count(struct ras_core_context *ras_core,
				     uint32_t *count, uint32_t timeout);
int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core,
					uint16_t index, uint64_t *mca_addr);
int ras_fw_set_timestamp(struct ras_core_context *ras_core,
				 uint64_t timestamp);
int ras_fw_get_timestamp(struct ras_core_context *ras_core,
				 uint16_t index, uint64_t *timestamp);
int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
				    uint16_t index, uint64_t *ipid);
int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
				   uint32_t *result);
int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
int ras_fw_eeprom_append(struct ras_core_context *ras_core,
			   struct eeprom_umc_record *record, const u32 num);
int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
			 struct eeprom_umc_record *record_umc,
			 struct ras_bank_ecc *ras_ecc,
			 u32 rec_idx, const u32 num);
uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core);
int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
				struct ras_bank_ecc *ras_ecc);
int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core);
int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core);
int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core);
enum ras_gpu_health_status
	ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core);
void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core);

#endif

Annotation

Implementation Notes