drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h- Extension
.h- Size
- 5376 bytes
- Lines
- 191
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
ras_sys.h
Detected Declarations
struct ras_eeprom_table_headerstruct ras_eeprom_table_ras_infostruct ras_eeprom_controlstruct eeprom_umc_recordstruct ras_core_contextenum ras_eeprom_err_type
Annotated Snippet
struct ras_eeprom_table_header {
uint32_t header;
uint32_t version;
uint32_t first_rec_offset;
uint32_t tbl_size;
uint32_t checksum;
} __packed;
struct ras_eeprom_table_ras_info {
u8 rma_status;
u8 health_percent;
u16 ecc_page_threshold;
u32 padding[64 - 1];
} __packed;
struct ras_eeprom_control {
struct ras_eeprom_table_header tbl_hdr;
struct ras_eeprom_table_ras_info tbl_rai;
/* record threshold */
int record_threshold_config;
uint32_t record_threshold_count;
bool update_channel_flag;
const struct ras_eeprom_sys_func *sys_func;
void *i2c_adapter;
u32 i2c_port;
u16 max_read_len;
u16 max_write_len;
/* Base I2C EEPPROM 19-bit memory address,
* where the table is located. For more information,
* see top of amdgpu_eeprom.c.
*/
u32 i2c_address;
/* The byte offset off of @i2c_address
* where the table header is found,
* and where the records start--always
* right after the header.
*/
u32 ras_header_offset;
u32 ras_info_offset;
u32 ras_record_offset;
/* Number of records in the table.
*/
u32 ras_num_recs;
/* First record index to read, 0-based.
* Range is [0, num_recs-1]. This is
* an absolute index, starting right after
* the table header.
*/
u32 ras_fri;
/* Maximum possible number of records
* we could store, i.e. the maximum capacity
* of the table.
*/
u32 ras_max_record_count;
/* Protect table access via this mutex.
*/
struct mutex ras_tbl_mutex;
/* Record channel info which occurred bad pages
*/
u32 bad_channel_bitmap;
};
/*
* Represents single table record. Packed to be easily serialized into byte
* stream.
*/
struct eeprom_umc_record {
union {
uint64_t address;
uint64_t offset;
};
uint64_t retired_row_pfn;
uint64_t ts;
enum ras_eeprom_err_type err_type;
union {
unsigned char bank;
unsigned char cu;
Annotation
- Immediate include surface: `ras_sys.h`.
- Detected declarations: `struct ras_eeprom_table_header`, `struct ras_eeprom_table_ras_info`, `struct ras_eeprom_control`, `struct eeprom_umc_record`, `struct ras_core_context`, `enum ras_eeprom_err_type`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.