drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h
Extension
.h
Size
9042 bytes
Lines
260
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __RAS_GFX_V9_0_H__
#define __RAS_GFX_V9_0_H__

enum ras_gfx_v9_subblock {
	/* CPC */
	RAS_GFX_V9__GFX_CPC_INDEX_START = 0,
	RAS_GFX_V9__GFX_CPC_SCRATCH =
		RAS_GFX_V9__GFX_CPC_INDEX_START,
	RAS_GFX_V9__GFX_CPC_UCODE,
	RAS_GFX_V9__GFX_DC_STATE_ME1,
	RAS_GFX_V9__GFX_DC_CSINVOC_ME1,
	RAS_GFX_V9__GFX_DC_RESTORE_ME1,
	RAS_GFX_V9__GFX_DC_STATE_ME2,
	RAS_GFX_V9__GFX_DC_CSINVOC_ME2,
	RAS_GFX_V9__GFX_DC_RESTORE_ME2,
	RAS_GFX_V9__GFX_CPC_INDEX_END =
		RAS_GFX_V9__GFX_DC_RESTORE_ME2,
	/* CPF */
	RAS_GFX_V9__GFX_CPF_INDEX_START,
	RAS_GFX_V9__GFX_CPF_ROQ_ME2 =
		RAS_GFX_V9__GFX_CPF_INDEX_START,
	RAS_GFX_V9__GFX_CPF_ROQ_ME1,
	RAS_GFX_V9__GFX_CPF_TAG,
	RAS_GFX_V9__GFX_CPF_INDEX_END = RAS_GFX_V9__GFX_CPF_TAG,
	/* CPG */
	RAS_GFX_V9__GFX_CPG_INDEX_START,
	RAS_GFX_V9__GFX_CPG_DMA_ROQ =
		RAS_GFX_V9__GFX_CPG_INDEX_START,
	RAS_GFX_V9__GFX_CPG_DMA_TAG,
	RAS_GFX_V9__GFX_CPG_TAG,
	RAS_GFX_V9__GFX_CPG_INDEX_END = RAS_GFX_V9__GFX_CPG_TAG,
	/* GDS */
	RAS_GFX_V9__GFX_GDS_INDEX_START,
	RAS_GFX_V9__GFX_GDS_MEM = RAS_GFX_V9__GFX_GDS_INDEX_START,
	RAS_GFX_V9__GFX_GDS_INPUT_QUEUE,
	RAS_GFX_V9__GFX_GDS_OA_PHY_CMD_RAM_MEM,
	RAS_GFX_V9__GFX_GDS_OA_PHY_DATA_RAM_MEM,
	RAS_GFX_V9__GFX_GDS_OA_PIPE_MEM,
	RAS_GFX_V9__GFX_GDS_INDEX_END =
		RAS_GFX_V9__GFX_GDS_OA_PIPE_MEM,
	/* SPI */
	RAS_GFX_V9__GFX_SPI_SR_MEM,
	/* SQ */
	RAS_GFX_V9__GFX_SQ_INDEX_START,
	RAS_GFX_V9__GFX_SQ_SGPR = RAS_GFX_V9__GFX_SQ_INDEX_START,
	RAS_GFX_V9__GFX_SQ_LDS_D,
	RAS_GFX_V9__GFX_SQ_LDS_I,
	RAS_GFX_V9__GFX_SQ_VGPR,
	RAS_GFX_V9__GFX_SQ_INDEX_END = RAS_GFX_V9__GFX_SQ_VGPR,
	/* SQC (3 ranges) */
	RAS_GFX_V9__GFX_SQC_INDEX_START,
	/* SQC range 0 */
	RAS_GFX_V9__GFX_SQC_INDEX0_START =
		RAS_GFX_V9__GFX_SQC_INDEX_START,
	RAS_GFX_V9__GFX_SQC_INST_UTCL1_LFIFO =
		RAS_GFX_V9__GFX_SQC_INDEX0_START,
	RAS_GFX_V9__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
	RAS_GFX_V9__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
	RAS_GFX_V9__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
	RAS_GFX_V9__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
	RAS_GFX_V9__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
	RAS_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
	RAS_GFX_V9__GFX_SQC_INDEX0_END =
		RAS_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
	/* SQC range 1 */
	RAS_GFX_V9__GFX_SQC_INDEX1_START,
	RAS_GFX_V9__GFX_SQC_INST_BANKA_TAG_RAM =
		RAS_GFX_V9__GFX_SQC_INDEX1_START,
	RAS_GFX_V9__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
	RAS_GFX_V9__GFX_SQC_INST_BANKA_MISS_FIFO,
	RAS_GFX_V9__GFX_SQC_INST_BANKA_BANK_RAM,
	RAS_GFX_V9__GFX_SQC_DATA_BANKA_TAG_RAM,
	RAS_GFX_V9__GFX_SQC_DATA_BANKA_HIT_FIFO,
	RAS_GFX_V9__GFX_SQC_DATA_BANKA_MISS_FIFO,
	RAS_GFX_V9__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
	RAS_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM,
	RAS_GFX_V9__GFX_SQC_INDEX1_END =
		RAS_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM,
	/* SQC range 2 */
	RAS_GFX_V9__GFX_SQC_INDEX2_START,
	RAS_GFX_V9__GFX_SQC_INST_BANKB_TAG_RAM =
		RAS_GFX_V9__GFX_SQC_INDEX2_START,
	RAS_GFX_V9__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
	RAS_GFX_V9__GFX_SQC_INST_BANKB_MISS_FIFO,
	RAS_GFX_V9__GFX_SQC_INST_BANKB_BANK_RAM,
	RAS_GFX_V9__GFX_SQC_DATA_BANKB_TAG_RAM,
	RAS_GFX_V9__GFX_SQC_DATA_BANKB_HIT_FIFO,
	RAS_GFX_V9__GFX_SQC_DATA_BANKB_MISS_FIFO,
	RAS_GFX_V9__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
	RAS_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM,

Annotation

Implementation Notes