drivers/gpu/drm/amd/ras/rascore/ras.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/rascore/ras.h
Extension
.h
Size
11845 bytes
Lines
402
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ras_mp1_sys_func {
	int (*mp1_get_valid_bank_count)(struct ras_core_context *ras_core,
			u32 msg, u32 *count);
	int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
			u32 msg, u32 idx, u32 reg_idx, u64 *val);
	int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
			enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg);
	int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
			uint64_t *enabled_mask);
};

struct ras_eeprom_sys_func {
	int (*eeprom_i2c_xfer)(struct ras_core_context *ras_core,
			u32 eeprom_addr, u8 *eeprom_buf, u32 buf_size, bool read);
	int (*update_eeprom_i2c_config)(struct ras_core_context *ras_core);
};

struct ras_nbio_sys_func {
	int (*set_ras_controller_irq_state)(struct ras_core_context *ras_core,
			bool state);
	int (*set_ras_err_event_athub_irq_state)(struct ras_core_context *ras_core,
			bool state);
};

struct ras_time {
	int tm_sec;
	int tm_min;
	int tm_hour;
	int tm_mday;
	int tm_mon;
	long tm_year;
};

struct device_system_info {
	uint32_t device_id;
	uint32_t vendor_id;
	uint32_t socket_id;
};

enum gpu_mem_type {
	GPU_MEM_TYPE_DEFAULT,
	GPU_MEM_TYPE_RAS_PSP_RING,
	GPU_MEM_TYPE_RAS_PSP_CMD,
	GPU_MEM_TYPE_RAS_PSP_FENCE,
	GPU_MEM_TYPE_RAS_TA_FW,
	GPU_MEM_TYPE_RAS_TA_CMD,
};

struct ras_psp_sys_func {
	int (*get_ras_psp_system_status)(struct ras_core_context *ras_core,
		struct ras_psp_sys_status *status);
	int (*get_ras_ta_init_param)(struct ras_core_context *ras_core,
		struct ras_ta_init_param *ras_ta_param);
};

struct ras_sys_func {
	int (*gpu_reset_lock)(struct ras_core_context *ras_core,
			bool down, bool try);
	int (*check_gpu_status)(struct ras_core_context *ras_core,
			uint32_t *status);
	int (*gen_seqno)(struct ras_core_context *ras_core,
			enum ras_seqno_type seqno_type, uint64_t *seqno);
	int (*async_handle_ras_event)(struct ras_core_context *ras_core, void *data);
	int (*ras_notifier)(struct ras_core_context *ras_core,
		    enum ras_notify_event event_id, void *data);
	u64 (*get_utc_second_timestamp)(struct ras_core_context *ras_core);
	int (*get_device_system_info)(struct ras_core_context *ras_core,
			struct device_system_info *dev_info);
	bool (*detect_ras_interrupt)(struct ras_core_context *ras_core);
	int (*get_gpu_mem)(struct ras_core_context *ras_core,
		enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem);
	int (*put_gpu_mem)(struct ras_core_context *ras_core,
		enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem);
};

struct ras_ecc_count {
	uint64_t new_ce_count;
	uint64_t total_ce_count;
	uint64_t new_ue_count;
	uint64_t total_ue_count;
	uint64_t new_de_count;
	uint64_t total_de_count;
};

struct ras_bank_ecc {
	uint32_t nps;
	uint64_t seq_no;
	uint64_t status;
	uint64_t ipid;
	uint64_t addr;

Annotation

Implementation Notes