drivers/gpu/drm/amd/ras/rascore/ras_process.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras_process.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/rascore/ras_process.c
Extension
.c
Size
8293 bytes
Lines
323
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (ecc_data.new_de_count) {
			detected_de_count += ecc_data.new_de_count;
			timeout = 0;
		} else {
			if (!timeout && event_count)
				timeout = AMDGPU_RAS_WAITING_DATA_READY;

			if (timeout) {
				if (!--timeout)
					break;

				msleep(1);
			}
		}
	} while (detected_de_count < event_count);

	if (detected_de_count && ras_core_gpu_is_rma(ras_core))
		ras_process_add_reset_gpu_event(ras_core, GPU_RESET_CAUSE_RMA);

	return 0;
}

static int ras_process_non_umc_event(struct ras_core_context *ras_core)
{
	struct ras_process *ras_proc = &ras_core->ras_proc;
	struct ras_event_req req;
	uint32_t event_count = kfifo_len(&ras_proc->event_fifo);
	uint32_t reset_flags = 0;
	int ret = 0, i;

	for (i = 0; i < event_count; i++) {
		memset(&req, 0, sizeof(req));
		ret = ras_process_get_event(ras_core, &req);
		if (!ret)
			continue;

		ras_core_event_notify(ras_core,
			RAS_EVENT_ID__POISON_CONSUMPTION, &req);

		reset_flags |= req.reset;

		if (req.reset == GPU_RESET_CAUSE_RMA)
			continue;

		if (req.reset)
			RAS_DEV_INFO(ras_core->dev,
				"{%llu} GPU reset for %s RAS poison consumption is issued!\n",
				req.seqno, ras_core_get_ras_block_name(req.block));
		else
			RAS_DEV_INFO(ras_core->dev,
				"{%llu} %s RAS poison consumption is issued!\n",
				req.seqno, ras_core_get_ras_block_name(req.block));
	}

	if (reset_flags) {
		ret = ras_core_event_notify(ras_core,
				RAS_EVENT_ID__RESET_GPU, &reset_flags);
		if (!ret && (reset_flags & GPU_RESET_CAUSE_RMA))
			return -RAS_CORE_GPU_IN_MODE1_RESET;
	}

	return ret;
}

int ras_process_handle_ras_event(struct ras_core_context *ras_core)
{
	struct ras_process *ras_proc = &ras_core->ras_proc;
	uint32_t umc_event_count;
	int ret;

	ret = ras_core_event_notify(ras_core,
			RAS_EVENT_ID__RAS_EVENT_PROC_BEGIN, NULL);
	if (ret)
		return ret;

	ras_aca_clear_fatal_flag(ras_core);
	ras_umc_log_pending_bad_bank(ras_core);

	do {
		umc_event_count = atomic_read(&ras_proc->umc_interrupt_count);
		ret = ras_process_umc_event(ras_core, umc_event_count);
		if (ret == -RAS_CORE_GPU_IN_MODE1_RESET)
			break;

		if (umc_event_count)
			atomic_sub(umc_event_count, &ras_proc->umc_interrupt_count);
	} while (atomic_read(&ras_proc->umc_interrupt_count));

	if ((ret != -RAS_CORE_GPU_IN_MODE1_RESET) &&
			(kfifo_len(&ras_proc->event_fifo)))

Annotation

Implementation Notes