drivers/gpu/drm/amd/ras/rascore/ras_umc.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras_umc.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/rascore/ras_umc.h
Extension
.h
Size
6572 bytes
Lines
184
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct umc_flip_bits {
	uint32_t flip_bits_in_pa[UMC_PA_FLIP_BITS_NUM];
	uint32_t flip_row_bit;
	uint32_t r13_in_pa;
	uint32_t bit_num;
};

struct umc_mca_addr {
	uint64_t err_addr;
	uint32_t ch_inst;
	uint32_t umc_inst;
	uint32_t node_inst;
	uint32_t socket_id;
};

struct umc_phy_addr {
	uint64_t pa;
	uint32_t bank;
	uint32_t channel_idx;
};

struct umc_bank_addr {
	uint32_t stack_id; /* SID */
	uint32_t bank_group;
	uint32_t bank;
	uint32_t row;
	uint32_t column;
	uint32_t channel;
	uint32_t subchannel; /* Also called Pseudochannel (PC) */
};

struct ras_umc_ip_func {
	int (*bank_to_eeprom_record)(struct ras_core_context *ras_core,
			struct ras_bank_ecc *bank, struct eeprom_umc_record *record);
	int (*eeprom_record_to_nps_record)(struct ras_core_context *ras_core,
			struct eeprom_umc_record *record, uint32_t nps);
	int (*eeprom_record_to_nps_pages)(struct ras_core_context *ras_core,
			struct eeprom_umc_record *record, uint32_t nps,
			uint64_t *pfns, uint32_t num);
	int (*bank_to_soc_pa)(struct ras_core_context *ras_core,
			struct umc_bank_addr bank_addr, uint64_t *soc_pa);
	int (*soc_pa_to_bank)(struct ras_core_context *ras_core,
			uint64_t soc_pa, struct umc_bank_addr *bank_addr);
	void (*mca_ipid_parse)(struct ras_core_context *ras_core, uint64_t ipid,
			uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid);
};

struct eeprom_store_record {
	/* point to data records array */
	struct eeprom_umc_record *bps;
	/* the count of entries */
	int count;
	/* the space can place new entries */
	int space_left;
};

struct ras_umc_err_data {
	struct eeprom_store_record rom_data;
	struct eeprom_store_record ram_data;
	enum umc_memory_partition_mode umc_nps_mode;
	uint64_t last_retired_pfn;
};

struct ras_umc {
	u32 umc_ip_version;
	u32 umc_vram_type;
	const struct ras_umc_ip_func *ip_func;
	struct radix_tree_root root;
	struct mutex  tree_lock;
	struct mutex  umc_lock;
	struct mutex  bank_log_lock;
	struct mutex  pending_ecc_lock;
	struct ras_umc_err_data umc_err_data;
	struct list_head pending_ecc_list;
	/* number of entries currently queued on pending_ecc_list */
	u32 pending_ecc_count;
	/* number of entries dropped because pending_ecc_list was full */
	u32 pending_ecc_dropped;
};

/*
 * Upper bound on entries that can be queued on pending_ecc_list while a
 * GPU reset is in progress. Beyond this, new ECC events are dropped to
 * prevent unbounded kernel memory growth in case of an ECC storm or
 * malicious/repeated UMC error injection.
 */
#define RAS_UMC_PENDING_ECC_MAX  8192

int ras_umc_sw_init(struct ras_core_context *ras);
int ras_umc_sw_fini(struct ras_core_context *ras);

Annotation

Implementation Notes