drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
Extension
.c
Size
17066 bytes
Lines
529
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright 2025 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "ras.h"
#include "ras_umc.h"
#include "ras_core_status.h"
#include "ras_umc_v12_0.h"

#define NumDieInterleaved 4

static const uint32_t umc_v12_0_channel_idx_tbl[]
	[UMC_V12_0_UMC_INSTANCE_NUM][UMC_V12_0_CHANNEL_INSTANCE_NUM] = {
	{{3,   7,   11,  15,  2,   6,   10,  14},  {1,   5,   9,   13,  0,   4,   8,   12},
	 {19,  23,  27,  31,  18,  22,  26,  30},  {17,  21,  25,  29,  16,  20,  24,  28}},
	{{47,  43,  39,  35,  46,  42,  38,  34},  {45,  41,  37,  33,  44,  40,  36,  32},
	 {63,  59,  55,  51,  62,  58,  54,  50},  {61,  57,  53,  49,  60,  56,  52,  48}},
	{{79,  75,  71,  67,  78,  74,  70,  66},  {77,  73,  69,  65,  76,  72,  68,  64},
	 {95,  91,  87,  83,  94,  90,  86,  82},  {93,  89,  85,  81,  92,  88,  84,  80}},
	{{99,  103, 107, 111, 98,  102, 106, 110}, {97,  101, 105, 109, 96,  100, 104, 108},
	 {115, 119, 123, 127, 114, 118, 122, 126}, {113, 117, 121, 125, 112, 116, 120, 124}}
};

/* mapping of MCA error address to normalized address */
static const uint32_t umc_v12_0_ma2na_mapping[] = {
	0,  5,  6,  8,  9,  14, 12, 13,
	10, 11, 15, 16, 17, 18, 19, 20,
	21, 22, 23, 24, 25, 26, 27, 28,
	24, 7,  29, 30,
};

static bool umc_v12_0_bit_wise_xor(uint32_t val)
{
	bool result = 0;
	int i;

	for (i = 0; i < 32; i++)
		result = result ^ ((val >> i) & 0x1);

	return result;
}

static void __get_nps_pa_flip_bits(struct ras_core_context *ras_core,
			enum umc_memory_partition_mode nps,
			struct umc_flip_bits *flip_bits)
{
	uint32_t vram_type = ras_core->ras_umc.umc_vram_type;

	/* default setting */
	flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT;
	flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT;
	flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT;
	flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT;
	flip_bits->flip_row_bit = 13;
	flip_bits->bit_num = 4;
	flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT;

	if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) {
		flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
		flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
		flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
		flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
	} else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) {
		flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
		flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
		flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
		flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
	}

	switch (vram_type) {
	case UMC_VRAM_TYPE_HBM:

Annotation

Implementation Notes