drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h
Extension
.h
Size
12744 bytes
Lines
315
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __RAS_UMC_V12_0_H__
#define __RAS_UMC_V12_0_H__
#include "ras.h"

/* MCA_UMC_UMC0_MCUMC_ADDRT0 */
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT                0x0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT                 0x38
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK                  0x00FFFFFFFFFFFFFFL
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK                   0xFF00000000000000L

/* MCMP1_IPIDT0 */
#define MCMP1_IPIDT0__InstanceIdLo__SHIFT                          0x0
#define MCMP1_IPIDT0__HardwareID__SHIFT                            0x20
#define MCMP1_IPIDT0__InstanceIdHi__SHIFT                          0x2c
#define MCMP1_IPIDT0__McaType__SHIFT                               0x30

#define MCMP1_IPIDT0__InstanceIdLo_MASK                            0x00000000FFFFFFFFL
#define MCMP1_IPIDT0__HardwareID_MASK                              0x00000FFF00000000L
#define MCMP1_IPIDT0__InstanceIdHi_MASK                            0x0000F00000000000L
#define MCMP1_IPIDT0__McaType_MASK                                 0xFFFF000000000000L

/* number of umc channel instance with memory map register access */
#define UMC_V12_0_CHANNEL_INSTANCE_NUM		8
/* number of umc instance with memory map register access */
#define UMC_V12_0_UMC_INSTANCE_NUM		4

/* one piece of normalized address is mapped to 8 pieces of physical address */
#define UMC_V12_0_NA_MAP_PA_NUM        8

/* bank bits in MCA error address */
#define UMC_V12_0_MCA_B0_BIT 6
#define UMC_V12_0_MCA_B1_BIT 7
#define UMC_V12_0_MCA_B2_BIT 8
#define UMC_V12_0_MCA_B3_BIT 9

/* row bits in MCA address */
#define UMC_V12_0_MCA_R0_BIT 10

/* Stack ID bits in SOC physical address */
#define UMC_V12_0_PA_SID1_BIT 37
#define UMC_V12_0_PA_SID0_BIT 36

/* bank bits in SOC physical address */
#define UMC_V12_0_PA_B3_BIT 18
#define UMC_V12_0_PA_B2_BIT 17
#define UMC_V12_0_PA_B1_BIT 20
#define UMC_V12_0_PA_B0_BIT 19

/* row bits in SOC physical address */
#define UMC_V12_0_PA_R13_BIT 35
#define UMC_V12_0_PA_R12_BIT 34
#define UMC_V12_0_PA_R11_BIT 33
#define UMC_V12_0_PA_R10_BIT 32
#define UMC_V12_0_PA_R9_BIT 31
#define UMC_V12_0_PA_R8_BIT 30
#define UMC_V12_0_PA_R7_BIT 29
#define UMC_V12_0_PA_R6_BIT 28
#define UMC_V12_0_PA_R5_BIT 27
#define UMC_V12_0_PA_R4_BIT 26
#define UMC_V12_0_PA_R3_BIT 25
#define UMC_V12_0_PA_R2_BIT 24
#define UMC_V12_0_PA_R1_BIT 23
#define UMC_V12_0_PA_R0_BIT 22

/* column bits in SOC physical address */
#define UMC_V12_0_PA_C4_BIT 21
#define UMC_V12_0_PA_C3_BIT 16
#define UMC_V12_0_PA_C2_BIT 15
#define UMC_V12_0_PA_C1_BIT 6
#define UMC_V12_0_PA_C0_BIT 5

/* channel index bits in SOC physical address */
#define UMC_V12_0_PA_CH6_BIT 14
#define UMC_V12_0_PA_CH5_BIT 13
#define UMC_V12_0_PA_CH4_BIT 12
#define UMC_V12_0_PA_CH3_BIT 11
#define UMC_V12_0_PA_CH2_BIT 10
#define UMC_V12_0_PA_CH1_BIT 9
#define UMC_V12_0_PA_CH0_BIT 8

/* Pseudochannel index bits in SOC physical address */
#define UMC_V12_0_PA_PC0_BIT 7

#define UMC_V12_0_NA_C2_BIT 8

#define UMC_V12_0_SOC_PA_TO_SID(pa) \
	((((pa >> UMC_V12_0_PA_SID0_BIT) & 0x1ULL) << 0ULL) | \
	 (((pa >> UMC_V12_0_PA_SID1_BIT) & 0x1ULL) << 1ULL))

#define UMC_V12_0_SOC_PA_TO_BANK(pa) \

Annotation

Implementation Notes