drivers/gpu/drm/arm/display/include/malidp_utils.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/arm/display/include/malidp_utils.h

Extension

.h

Size

975 bytes

Lines

44

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/delay.h
• linux/errno.h

Detected Declarations

• struct malidp_range
• function set_range
• function malidp_in_range

Annotated Snippet

struct malidp_range {
	u32 start;
	u32 end;
};

static inline void set_range(struct malidp_range *rg, u32 start, u32 end)
{
	rg->start = start;
	rg->end   = end;
}

static inline bool malidp_in_range(struct malidp_range *rg, u32 v)
{
	return (v >= rg->start) && (v <= rg->end);
}

#endif /* _MALIDP_UTILS_ */

Annotation

• Immediate include surface: `linux/delay.h`, `linux/errno.h`.
• Detected declarations: `struct malidp_range`, `function set_range`, `function malidp_in_range`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.