drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h- Extension
.h- Size
- 14374 bytes
- Lines
- 542
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct block_headerenum d71_blk_typefunction get_block_type
Annotated Snippet
struct block_header {
u32 block_info;
u32 pipeline_info;
u32 input_ids[D71_BLOCK_MAX_INPUT];
u32 output_ids[D71_BLOCK_MAX_OUTPUT];
};
static inline u32 get_block_type(struct block_header *blk)
{
return BLOCK_INFO_BLK_TYPE(blk->block_info);
}
#endif /* !_D71_REG_H_ */
Annotation
- Detected declarations: `struct block_header`, `enum d71_blk_type`, `function get_block_type`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.