drivers/gpu/drm/armada/armada_hw.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/armada/armada_hw.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/armada/armada_hw.h
Extension
.h
Size
8874 bytes
Lines
331
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ARMADA_HW_H
#define ARMADA_HW_H

/*
 * Note: the following registers are written from IRQ context:
 *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
 *  LCD_SPU_DMA_START_ADDR_[YUV][01], LCD_SPU_DMA_PITCH_YC,
 *  LCD_SPU_DMA_PITCH_UV, LCD_SPU_DMA_OVSA_HPXL_VLN,
 *  LCD_SPU_DMA_HPXL_VLN, LCD_SPU_DZM_HPXL_VLN, LCD_SPU_DMA_CTRL0
 */
enum {
	LCD_SPU_ADV_REG			= 0x0084,	/* Armada 510 */
	LCD_SPU_DMA_START_ADDR_Y0	= 0x00c0,
	LCD_SPU_DMA_START_ADDR_U0	= 0x00c4,
	LCD_SPU_DMA_START_ADDR_V0	= 0x00c8,
	LCD_CFG_DMA_START_ADDR_0	= 0x00cc,
	LCD_SPU_DMA_START_ADDR_Y1	= 0x00d0,
	LCD_SPU_DMA_START_ADDR_U1	= 0x00d4,
	LCD_SPU_DMA_START_ADDR_V1	= 0x00d8,
	LCD_CFG_DMA_START_ADDR_1	= 0x00dc,
	LCD_SPU_DMA_PITCH_YC		= 0x00e0,
	LCD_SPU_DMA_PITCH_UV		= 0x00e4,
	LCD_SPU_DMA_OVSA_HPXL_VLN	= 0x00e8,
	LCD_SPU_DMA_HPXL_VLN		= 0x00ec,
	LCD_SPU_DZM_HPXL_VLN		= 0x00f0,
	LCD_CFG_GRA_START_ADDR0		= 0x00f4,
	LCD_CFG_GRA_START_ADDR1		= 0x00f8,
	LCD_CFG_GRA_PITCH		= 0x00fc,
	LCD_SPU_GRA_OVSA_HPXL_VLN	= 0x0100,
	LCD_SPU_GRA_HPXL_VLN		= 0x0104,
	LCD_SPU_GZM_HPXL_VLN		= 0x0108,
	LCD_SPU_HWC_OVSA_HPXL_VLN	= 0x010c,
	LCD_SPU_HWC_HPXL_VLN		= 0x0110,
	LCD_SPUT_V_H_TOTAL		= 0x0114,
	LCD_SPU_V_H_ACTIVE		= 0x0118,
	LCD_SPU_H_PORCH			= 0x011c,
	LCD_SPU_V_PORCH			= 0x0120,
	LCD_SPU_BLANKCOLOR		= 0x0124,
	LCD_SPU_ALPHA_COLOR1		= 0x0128,
	LCD_SPU_ALPHA_COLOR2		= 0x012c,
	LCD_SPU_COLORKEY_Y		= 0x0130,
	LCD_SPU_COLORKEY_U		= 0x0134,
	LCD_SPU_COLORKEY_V		= 0x0138,
	LCD_CFG_RDREG4F			= 0x013c,	/* Armada 510 */
	LCD_SPU_SPI_RXDATA		= 0x0140,
	LCD_SPU_ISA_RXDATA		= 0x0144,
	LCD_SPU_HWC_RDDAT		= 0x0158,
	LCD_SPU_GAMMA_RDDAT		= 0x015c,
	LCD_SPU_PALETTE_RDDAT		= 0x0160,
	LCD_SPU_IOPAD_IN		= 0x0178,
	LCD_CFG_RDREG5F			= 0x017c,
	LCD_SPU_SPI_CTRL		= 0x0180,
	LCD_SPU_SPI_TXDATA		= 0x0184,
	LCD_SPU_SMPN_CTRL		= 0x0188,
	LCD_SPU_DMA_CTRL0		= 0x0190,
	LCD_SPU_DMA_CTRL1		= 0x0194,
	LCD_SPU_SRAM_CTRL		= 0x0198,
	LCD_SPU_SRAM_WRDAT		= 0x019c,
	LCD_SPU_SRAM_PARA0		= 0x01a0,	/* Armada 510 */
	LCD_SPU_SRAM_PARA1		= 0x01a4,
	LCD_CFG_SCLK_DIV		= 0x01a8,
	LCD_SPU_CONTRAST		= 0x01ac,
	LCD_SPU_SATURATION		= 0x01b0,
	LCD_SPU_CBSH_HUE		= 0x01b4,
	LCD_SPU_DUMB_CTRL		= 0x01b8,
	LCD_SPU_IOPAD_CONTROL		= 0x01bc,
	LCD_SPU_IRQ_ENA			= 0x01c0,
	LCD_SPU_IRQ_ISR			= 0x01c4,
};

/* For LCD_SPU_ADV_REG */
enum {
	ADV_VSYNC_L_OFF	= 0xfff << 20,
	ADV_GRACOLORKEY	= 1 << 19,
	ADV_VIDCOLORKEY	= 1 << 18,
	ADV_HWC32BLEND	= 1 << 15,
	ADV_HWC32ARGB	= 1 << 14,
	ADV_HWC32ENABLE	= 1 << 13,
	ADV_VSYNCOFFEN	= 1 << 12,
	ADV_VSYNC_H_OFF	= 0xfff << 0,
};

/* LCD_CFG_RDREG4F - Armada 510 only */
enum {
	CFG_SRAM_WAIT	= BIT(11),
	CFG_SMPN_FASTTX	= BIT(10),
	CFG_DMA_ARB	= BIT(9),
	CFG_DMA_WM_EN	= BIT(8),
	CFG_DMA_WM_MASK	= 0xff,
#define CFG_DMA_WM(x)	((x) & CFG_DMA_WM_MASK)

Annotation

Implementation Notes