drivers/gpu/drm/ast/ast_reg.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/ast/ast_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/ast/ast_reg.h
Extension
.h
Size
9661 bytes
Lines
266
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __AST_REG_H__
#define __AST_REG_H__

#include <linux/bits.h>

/*
 * Modesetting
 */

#define AST_IO_MM_OFFSET		(0x380)
#define AST_IO_MM_LENGTH		(128)

#define AST_IO_VGAARI_W			(0x40)

#define AST_IO_VGAMR_W			(0x42)
#define AST_IO_VGAMR_R			(0x4c)
#define AST_IO_VGAMR_IOSEL		BIT(0)

#define AST_IO_VGAER			(0x43)
#define AST_IO_VGAER_VGA_ENABLE		BIT(0)

#define AST_IO_VGASRI			(0x44)
#define AST_IO_VGASR1_SD		BIT(5)
#define AST_IO_VGADRR			(0x47)
#define AST_IO_VGADWR			(0x48)
#define AST_IO_VGAPDR		        (0x49)
#define AST_IO_VGAGRI			(0x4E)

#define AST_IO_VGACRI				(0x54)
#define AST_IO_VGACR17_SYNC_ENABLE		BIT(7) /* called "Hardware reset" in docs */
#define AST_IO_VGACR80_PASSWORD			(0xa8)

#define AST_IO_VGACR8C_NEW_MODE_MASK		GENMASK(3, 0)
#define AST_IO_VGACR8C_NEW_MODE_EGA		(0x00)
#define AST_IO_VGACR8C_NEW_MODE_VGA		(0x01)
#define AST_IO_VGACR8C_NEW_MODE_15_BPP		(0x02)
#define AST_IO_VGACR8C_NEW_MODE_16_BPP		(0x03)
#define AST_IO_VGACR8C_NEW_MODE_32_BPP		(0x04)
#define AST_IO_VGACR8C_NEW_MODE_CGA		(0x0f)
#define AST_IO_VGACR8C_NEW_MODE_TEXT		(0x0e)
#define AST_IO_VGACR8C_CUR_MODE_MASK		GENMASK(7, 4)
#define AST_IO_VGACR8C_CUR_MODE_EGA		(0x00)
#define AST_IO_VGACR8C_CUR_MODE_VGA		(0x10)
#define AST_IO_VGACR8C_CUR_MODE_15_BPP		(0x20)
#define AST_IO_VGACR8C_CUR_MODE_16_BPP		(0x30)
#define AST_IO_VGACR8C_CUR_MODE_32_BPP		(0x40)
#define AST_IO_VGACR8C_CUR_MODE_CGA		(0xf0)
#define AST_IO_VGACR8C_CUR_MODE_TEXT		(0xe0)

#define AST_IO_VGACR91_PASSWORD			(0xa8)
#define AST_IO_VGACR99_VGAMEM_RSRV_MASK		GENMASK(1, 0)

#define AST_IO_VGACRA0_MEMORY_CHAIN4_MODE	BIT(6)
#define AST_IO_VGACRA0_LINEAR_EXT_ACCESS	BIT(5)
#define AST_IO_VGACRA0_SEGMENTED_EXT_ACCESS	BIT(4)

#define AST_IO_VGACRA1_VGAIO_DISABLED		BIT(1)
#define AST_IO_VGACRA1_MMIO_ENABLED		BIT(2)

#define AST_IO_VGACRA3_DVO_ENABLED		BIT(7)
#define AST_IO_VGACRA3_32_BPP			BIT(3)
#define AST_IO_VGACRA3_16_BPP			BIT(2)
#define AST_IO_VGACRA3_15_BPP			BIT(1)
#define AST_IO_VGACRA3_256_COLORS		BIT(0)

#define AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED	BIT(1)
#define AST_IO_VGACRAA_VGAMEM_SIZE_MASK		GENMASK(1, 0)
#define AST_IO_VGACRB6_HSYNC_OFF		BIT(0)
#define AST_IO_VGACRB6_VSYNC_OFF		BIT(1)
#define AST_IO_VGACRCB_HWC_16BPP		BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
#define AST_IO_VGACRCB_HWC_ENABLED		BIT(1)

/* mirrors SCU100[7:0] */
#define AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
#define AST_IO_VGACRD0_VRAM_INIT_BY_BMC		BIT(7)
#define AST_IO_VGACRD0_VRAM_INIT_READY		BIT(6)
#define AST_IO_VGACRD0_IKVM_WIDESCREEN		BIT(0)

#define AST_IO_VGACRD1_MCU_FW_EXECUTING		BIT(5)
/* Display Transmitter Type */
#define AST_IO_VGACRD1_TX_TYPE_MASK		GENMASK(3, 1)
#define AST_IO_VGACRD1_NO_TX			0x00
#define AST_IO_VGACRD1_TX_ITE66121_VBIOS	0x02
#define AST_IO_VGACRD1_TX_SIL164_VBIOS		0x04
#define AST_IO_VGACRD1_TX_CH7003_VBIOS		0x06
#define AST_IO_VGACRD1_TX_DP501_VBIOS		0x08
#define AST_IO_VGACRD1_TX_ANX9807_VBIOS		0x0a
#define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW	0x0c /* special case of DP501 */
#define AST_IO_VGACRD1_TX_ASTDP			0x0e
#define AST_IO_VGACRD1_SUPPORTS_WUXGA		BIT(0)

Annotation

Implementation Notes