drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/bridge/analogix/analogix-anx78xx.h
Extension
.h
Size
6731 bytes
Lines
250
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ANX78xx_H
#define __ANX78xx_H

#include "analogix-i2c-dptx.h"
#include "analogix-i2c-txcommon.h"

/***************************************************************/
/* Register definitions for RX_PO                              */
/***************************************************************/

/*
 * System Control and Status
 */

/* Software Reset Register 1 */
#define SP_SOFTWARE_RESET1_REG		0x11
#define SP_VIDEO_RST			BIT(4)
#define SP_HDCP_MAN_RST			BIT(2)
#define SP_TMDS_RST			BIT(1)
#define SP_SW_MAN_RST			BIT(0)

/* System Status Register */
#define SP_SYSTEM_STATUS_REG		0x14
#define SP_TMDS_CLOCK_DET		BIT(1)
#define SP_TMDS_DE_DET			BIT(0)

/* HDMI Status Register */
#define SP_HDMI_STATUS_REG		0x15
#define SP_HDMI_AUD_LAYOUT		BIT(3)
#define SP_HDMI_DET			BIT(0)
#  define SP_DVI_MODE			0
#  define SP_HDMI_MODE			1

/* HDMI Mute Control Register */
#define SP_HDMI_MUTE_CTRL_REG		0x16
#define SP_AUD_MUTE			BIT(1)
#define SP_VID_MUTE			BIT(0)

/* System Power Down Register 1 */
#define SP_SYSTEM_POWER_DOWN1_REG	0x18
#define SP_PWDN_CTRL			BIT(0)

/*
 * Audio and Video Auto Control
 */

/* Auto Audio and Video Control register */
#define SP_AUDVID_CTRL_REG		0x20
#define SP_AVC_OE			BIT(7)
#define SP_AAC_OE			BIT(6)
#define SP_AVC_EN			BIT(1)
#define SP_AAC_EN			BIT(0)

/* Audio Exception Enable Registers */
#define SP_AUD_EXCEPTION_ENABLE_BASE	(0x24 - 1)
/* Bits for Audio Exception Enable Register 3 */
#define SP_AEC_EN21			BIT(5)

/*
 * Interrupt
 */

/* Interrupt Status Register 1 */
#define SP_INT_STATUS1_REG		0x31
/* Bits for Interrupt Status Register 1 */
#define SP_HDMI_DVI			BIT(7)
#define SP_CKDT_CHG			BIT(6)
#define SP_SCDT_CHG			BIT(5)
#define SP_PCLK_CHG			BIT(4)
#define SP_PLL_UNLOCK			BIT(3)
#define SP_CABLE_PLUG_CHG		BIT(2)
#define SP_SET_MUTE			BIT(1)
#define SP_SW_INTR			BIT(0)
/* Bits for Interrupt Status Register 2 */
#define SP_HDCP_ERR			BIT(5)
#define SP_AUDIO_SAMPLE_CHG		BIT(0)	/* undocumented */
/* Bits for Interrupt Status Register 3 */
#define SP_AUD_MODE_CHG			BIT(0)
/* Bits for Interrupt Status Register 5 */
#define SP_AUDIO_RCV			BIT(0)
/* Bits for Interrupt Status Register 6 */
#define SP_INT_STATUS6_REG		0x36
#define SP_CTS_RCV			BIT(7)
#define SP_NEW_AUD_PKT			BIT(4)
#define SP_NEW_AVI_PKT			BIT(1)
#define SP_NEW_CP_PKT			BIT(0)
/* Bits for Interrupt Status Register 7 */
#define SP_NO_VSI			BIT(7)
#define SP_NEW_VS			BIT(4)

Annotation

Implementation Notes