drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
Extension
.h
Size
7351 bytes
Lines
257
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ANALOGIX_I2C_DPTX_H_
#define _ANALOGIX_I2C_DPTX_H_

/***************************************************************/
/* Register definitions for TX_P0                              */
/***************************************************************/

/* HDCP Status Register */
#define SP_TX_HDCP_STATUS_REG		0x00
#define SP_AUTH_FAIL			BIT(5)
#define SP_AUTHEN_PASS			BIT(1)

/* HDCP Control Register 0 */
#define SP_HDCP_CTRL0_REG		0x01
#define SP_RX_REPEATER			BIT(6)
#define SP_RE_AUTH			BIT(5)
#define SP_SW_AUTH_OK			BIT(4)
#define SP_HARD_AUTH_EN			BIT(3)
#define SP_HDCP_ENC_EN			BIT(2)
#define SP_BKSV_SRM_PASS		BIT(1)
#define SP_KSVLIST_VLD			BIT(0)
/* HDCP Function Enabled */
#define SP_HDCP_FUNCTION_ENABLED	(BIT(0) | BIT(1) | BIT(2) | BIT(3))

/* HDCP Receiver BSTATUS Register 0 */
#define	SP_HDCP_RX_BSTATUS0_REG		0x1b
/* HDCP Receiver BSTATUS Register 1 */
#define	SP_HDCP_RX_BSTATUS1_REG		0x1c

/* HDCP Embedded "Blue Screen" Content Registers */
#define SP_HDCP_VID0_BLUE_SCREEN_REG	0x2c
#define SP_HDCP_VID1_BLUE_SCREEN_REG	0x2d
#define SP_HDCP_VID2_BLUE_SCREEN_REG	0x2e

/* HDCP Wait R0 Timing Register */
#define SP_HDCP_WAIT_R0_TIME_REG	0x40

/* HDCP Link Integrity Check Timer Register */
#define SP_HDCP_LINK_CHECK_TIMER_REG	0x41

/* HDCP Repeater Ready Wait Timer Register */
#define SP_HDCP_RPTR_RDY_WAIT_TIME_REG	0x42

/* HDCP Auto Timer Register */
#define SP_HDCP_AUTO_TIMER_REG		0x51

/* HDCP Key Status Register */
#define SP_HDCP_KEY_STATUS_REG		0x5e

/* HDCP Key Command Register */
#define SP_HDCP_KEY_COMMAND_REG		0x5f
#define SP_DISABLE_SYNC_HDCP		BIT(2)

/* OTP Memory Key Protection Registers */
#define SP_OTP_KEY_PROTECT1_REG		0x60
#define SP_OTP_KEY_PROTECT2_REG		0x61
#define SP_OTP_KEY_PROTECT3_REG		0x62
#define SP_OTP_PSW1			0xa2
#define SP_OTP_PSW2			0x7e
#define SP_OTP_PSW3			0xc6

/* DP System Control Registers */
#define SP_DP_SYSTEM_CTRL_BASE		(0x80 - 1)
/* Bits for DP System Control Register 2 */
#define SP_CHA_STA			BIT(2)
/* Bits for DP System Control Register 3 */
#define SP_HPD_STATUS			BIT(6)
#define SP_HPD_FORCE			BIT(5)
#define SP_HPD_CTRL			BIT(4)
#define SP_STRM_VALID			BIT(2)
#define SP_STRM_FORCE			BIT(1)
#define SP_STRM_CTRL			BIT(0)
/* Bits for DP System Control Register 4 */
#define SP_ENHANCED_MODE		BIT(3)

/* DP Video Control Register */
#define SP_DP_VIDEO_CTRL_REG		0x84
#define SP_COLOR_F_MASK			0x06
#define SP_COLOR_F_SHIFT		1
#define SP_BPC_MASK			0xe0
#define SP_BPC_SHIFT			5
#  define SP_BPC_6BITS			0x00
#  define SP_BPC_8BITS			0x01
#  define SP_BPC_10BITS			0x02
#  define SP_BPC_12BITS			0x03

/* DP Audio Control Register */
#define SP_DP_AUDIO_CTRL_REG		0x87
#define SP_AUD_EN			BIT(0)

Annotation

Implementation Notes