drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.dtso

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.dtso

Extension

.dtso

Size

572 bytes

Lines

31

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: drivers/gpu

Status

atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * DTS overlay adding an hdmi-connector node to boards using the imx8mp hdmi_tx
 *
 * Copyright (C) 2026 GE HealthCare
 * Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
 */

/dts-v1/;
/plugin/;

&{/} {
	fixup-hdmi-connector {
		compatible = "hdmi-connector";
		label = "HDMI";
		type = "a";

		port {
			fixup_hdmi_connector_in: endpoint {
				remote-endpoint = <&hdmi_tx_out>;
			};
		};
	};
};

&{/soc@0/bus@32c00000/hdmi@32fd8000/ports/port@1} {
	hdmi_tx_out: endpoint {
		remote-endpoint = <&fixup_hdmi_connector_in>;
	};
};

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.