drivers/gpu/drm/bridge/sil-sii8620.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/bridge/sil-sii8620.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/bridge/sil-sii8620.h
Extension
.h
Size
52162 bytes
Lines
1533
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SIL_SII8620_H__
#define __SIL_SII8620_H__

/* Vendor ID Low byte, default value: 0x01 */
#define REG_VND_IDL				0x0000

/* Vendor ID High byte, default value: 0x00 */
#define REG_VND_IDH				0x0001

/* Device ID Low byte, default value: 0x60 */
#define REG_DEV_IDL				0x0002

/* Device ID High byte, default value: 0x86 */
#define REG_DEV_IDH				0x0003

/* Device Revision, default value: 0x10 */
#define REG_DEV_REV				0x0004

/* OTP DBYTE510, default value: 0x00 */
#define REG_OTP_DBYTE510			0x0006

/* System Control #1, default value: 0x00 */
#define REG_SYS_CTRL1				0x0008
#define BIT_SYS_CTRL1_OTPVMUTEOVR_SET		BIT(7)
#define BIT_SYS_CTRL1_VSYNCPIN			BIT(6)
#define BIT_SYS_CTRL1_OTPADROPOVR_SET		BIT(5)
#define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD		BIT(4)
#define BIT_SYS_CTRL1_OTP2XVOVR_EN		BIT(3)
#define BIT_SYS_CTRL1_OTP2XAOVR_EN		BIT(2)
#define BIT_SYS_CTRL1_TX_CTRL_HDMI		BIT(1)
#define BIT_SYS_CTRL1_OTPAMUTEOVR_SET		BIT(0)

/* System Control DPD, default value: 0x90 */
#define REG_DPD					0x000b
#define BIT_DPD_PWRON_PLL			BIT(7)
#define BIT_DPD_PDNTX12				BIT(6)
#define BIT_DPD_PDNRX12				BIT(5)
#define BIT_DPD_OSC_EN				BIT(4)
#define BIT_DPD_PWRON_HSIC			BIT(3)
#define BIT_DPD_PDIDCK_N			BIT(2)
#define BIT_DPD_PD_MHL_CLK_N			BIT(1)

/* Dual link Control, default value: 0x00 */
#define REG_DCTL				0x000d
#define BIT_DCTL_TDM_LCLK_PHASE			BIT(7)
#define BIT_DCTL_HSIC_CLK_PHASE			BIT(6)
#define BIT_DCTL_CTS_TCK_PHASE			BIT(5)
#define BIT_DCTL_EXT_DDC_SEL			BIT(4)
#define BIT_DCTL_TRANSCODE			BIT(3)
#define BIT_DCTL_HSIC_RX_STROBE_PHASE		BIT(2)
#define BIT_DCTL_HSIC_TX_BIST_START_SEL		BIT(1)
#define BIT_DCTL_TCLKNX_PHASE			BIT(0)

/* PWD Software Reset, default value: 0x20 */
#define REG_PWD_SRST				0x000e
#define BIT_PWD_SRST_COC_DOC_RST		BIT(7)
#define BIT_PWD_SRST_CBUS_RST_SW		BIT(6)
#define BIT_PWD_SRST_CBUS_RST_SW_EN		BIT(5)
#define BIT_PWD_SRST_MHLFIFO_RST		BIT(4)
#define BIT_PWD_SRST_CBUS_RST			BIT(3)
#define BIT_PWD_SRST_SW_RST_AUTO		BIT(2)
#define BIT_PWD_SRST_HDCP2X_SW_RST		BIT(1)
#define BIT_PWD_SRST_SW_RST			BIT(0)

/* AKSV_1, default value: 0x00 */
#define REG_AKSV_1				0x001d

/* Video H Resolution #1, default value: 0x00 */
#define REG_H_RESL				0x003a

/* Video Mode, default value: 0x00 */
#define REG_VID_MODE				0x004a
#define BIT_VID_MODE_M1080P			BIT(6)

/* Video Input Mode, default value: 0xc0 */
#define REG_VID_OVRRD				0x0051
#define BIT_VID_OVRRD_PP_AUTO_DISABLE		BIT(7)
#define BIT_VID_OVRRD_M1080P_OVRRD		BIT(6)
#define BIT_VID_OVRRD_MINIVSYNC_ON		BIT(5)
#define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK	BIT(4)
#define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN	BIT(3)
#define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD		BIT(2)
#define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD	BIT(0)

/* I2C Address reassignment, default value: 0x00 */
#define REG_PAGE_MHLSPEC_ADDR			0x0057
#define REG_PAGE7_ADDR				0x0058
#define REG_PAGE8_ADDR				0x005c

/* Fast Interrupt Status, default value: 0x00 */

Annotation

Implementation Notes