drivers/gpu/drm/bridge/synopsys/dw-dp.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/bridge/synopsys/dw-dp.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/bridge/synopsys/dw-dp.c- Extension
.c- Size
- 54044 bytes
- Lines
- 2099
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/clk.hlinux/iopoll.hlinux/irq.hlinux/media-bus-format.hlinux/of_device.hlinux/platform_device.hlinux/regmap.hlinux/reset.hlinux/phy/phy.hlinux/unaligned.hdrm/bridge/dw_dp.hdrm/drm_atomic_helper.hdrm/drm_bridge.hdrm/drm_bridge_connector.hdrm/display/drm_dp_helper.hdrm/drm_edid.hdrm/drm_of.hdrm/drm_print.hdrm/drm_probe_helper.hdrm/drm_simple_kms_helper.h
Detected Declarations
struct dw_dp_link_capsstruct dw_dp_link_train_setstruct dw_dp_link_trainstruct dw_dp_linkstruct dw_dp_bridge_statestruct dw_dp_sdpstruct dw_dp_hotplugstruct dw_dpstruct dw_dp_output_formatfunction dw_dp_phy_set_patternfunction dw_dp_phy_xmit_enablefunction dw_dp_bandwidth_okfunction dw_dp_hpd_detectfunction dw_dp_link_caps_resetfunction dw_dp_link_resetfunction dw_dp_link_parsefunction dw_dp_link_train_update_vs_emphfunction dw_dp_phy_configurefunction dw_dp_link_configurefunction dw_dp_link_train_initfunction dw_dp_link_train_validfunction dw_dp_link_train_set_patternfunction dw_dp_voltage_maxfunction dw_dp_link_get_adjustmentsfunction dw_dp_link_clock_recoveryfunction dw_dp_link_channel_equalizationfunction dw_dp_link_downgradefunction dw_dp_link_train_fullfunction dw_dp_link_train_fastfunction dw_dp_link_trainfunction dw_dp_send_sdpfunction dw_dp_send_vsc_sdpfunction dw_dp_video_set_pixel_modefunction dw_dp_video_need_vsc_sdpfunction dw_dp_video_set_msafunction dw_dp_video_disablefunction dw_dp_video_enablefunction dw_dp_hpd_initfunction dw_dp_aux_initfunction dw_dp_init_hwfunction dw_dp_aux_write_datafunction dw_dp_aux_read_datafunction dw_dp_aux_transferfunction dw_dp_bridge_atomic_checkfunction dw_dp_bridge_mode_validfunction dw_dp_needs_link_retrainfunction dw_dp_link_disablefunction dw_dp_link_enable
Annotated Snippet
struct dw_dp_link_caps {
bool enhanced_framing;
bool tps3_supported;
bool tps4_supported;
bool fast_training;
bool channel_coding;
bool ssc;
};
struct dw_dp_link_train_set {
unsigned int voltage_swing[4];
unsigned int pre_emphasis[4];
bool voltage_max_reached[4];
bool pre_max_reached[4];
};
struct dw_dp_link_train {
struct dw_dp_link_train_set adjust;
bool clock_recovered;
bool channel_equalized;
};
struct dw_dp_link {
u8 dpcd[DP_RECEIVER_CAP_SIZE];
unsigned char revision;
unsigned int rate;
unsigned int lanes;
u8 sink_count;
u8 vsc_sdp_supported;
struct dw_dp_link_caps caps;
struct dw_dp_link_train train;
struct drm_dp_desc desc;
};
struct dw_dp_bridge_state {
struct drm_bridge_state base;
struct drm_display_mode mode;
u8 video_mapping;
u8 color_format;
u8 bpc;
u8 bpp;
};
struct dw_dp_sdp {
struct dp_sdp base;
unsigned long flags;
};
struct dw_dp_hotplug {
bool long_hpd;
};
struct dw_dp {
struct drm_bridge bridge;
struct device *dev;
struct regmap *regmap;
struct phy *phy;
struct clk *apb_clk;
struct clk *aux_clk;
struct clk *i2s_clk;
struct clk *spdif_clk;
struct clk *hdcp_clk;
struct reset_control *rstc;
struct completion complete;
int irq;
struct work_struct hpd_work;
struct dw_dp_hotplug hotplug;
/* Serialize hpd status access */
struct mutex irq_lock;
struct drm_dp_aux aux;
struct dw_dp_link link;
struct dw_dp_plat_data plat_data;
u8 pixel_mode;
DECLARE_BITMAP(sdp_reg_bank, SDP_REG_BANK_SIZE);
};
enum {
DW_DP_RGB_6BIT,
DW_DP_RGB_8BIT,
DW_DP_RGB_10BIT,
DW_DP_RGB_12BIT,
DW_DP_RGB_16BIT,
DW_DP_YCBCR444_8BIT,
DW_DP_YCBCR444_10BIT,
DW_DP_YCBCR444_12BIT,
DW_DP_YCBCR444_16BIT,
DW_DP_YCBCR422_8BIT,
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/clk.h`, `linux/iopoll.h`, `linux/irq.h`, `linux/media-bus-format.h`, `linux/of_device.h`, `linux/platform_device.h`, `linux/regmap.h`.
- Detected declarations: `struct dw_dp_link_caps`, `struct dw_dp_link_train_set`, `struct dw_dp_link_train`, `struct dw_dp_link`, `struct dw_dp_bridge_state`, `struct dw_dp_sdp`, `struct dw_dp_hotplug`, `struct dw_dp`, `struct dw_dp_output_format`, `function dw_dp_phy_set_pattern`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.