drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h
Extension
.h
Size
33253 bytes
Lines
852
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DW_HDMI_QP_H__
#define __DW_HDMI_QP_H__

#include <linux/bits.h>

/* Main Unit Registers */
#define CORE_ID						0x0
#define VER_NUMBER					0x4
#define VER_TYPE					0x8
#define CONFIG_REG					0xc
#define CONFIG_CEC					BIT(28)
#define CONFIG_AUD_UD					BIT(23)
#define CORE_TIMESTAMP_HHMM				0x14
#define CORE_TIMESTAMP_MMDD				0x18
#define CORE_TIMESTAMP_YYYY				0x1c
/* Reset Manager Registers */
#define GLOBAL_SWRESET_REQUEST				0x40
#define EARCRX_CMDC_SWINIT_P				BIT(27)
#define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P		BIT(10)
#define GLOBAL_SWDISABLE				0x44
#define CEC_SWDISABLE					BIT(17)
#define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE		BIT(10)
#define AVP_DATAPATH_VIDEO_SWDISABLE			BIT(6)
#define RESET_MANAGER_CONFIG0				0x48
#define RESET_MANAGER_STATUS0				0x50
#define RESET_MANAGER_STATUS1				0x54
#define RESET_MANAGER_STATUS2				0x58
/* Timer Base Registers */
#define TIMER_BASE_CONFIG0				0x80
#define TIMER_BASE_STATUS0				0x84
/* CMU Registers */
#define CMU_CONFIG0					0xa0
#define CMU_CONFIG1					0xa4
#define CMU_CONFIG2					0xa8
#define CMU_CONFIG3					0xac
#define CMU_STATUS					0xb0
#define DISPLAY_CLK_MONITOR				0x3f
#define DISPLAY_CLK_LOCKED				0X15
#define EARC_BPCLK_OFF					BIT(9)
#define AUDCLK_OFF					BIT(7)
#define LINKQPCLK_OFF					BIT(5)
#define VIDQPCLK_OFF					BIT(3)
#define IPI_CLK_OFF					BIT(1)
#define CMU_IPI_CLK_FREQ				0xb4
#define CMU_VIDQPCLK_FREQ				0xb8
#define CMU_LINKQPCLK_FREQ				0xbc
#define CMU_AUDQPCLK_FREQ				0xc0
#define CMU_EARC_BPCLK_FREQ				0xc4
/* I2CM Registers */
#define I2CM_SM_SCL_CONFIG0				0xe0
#define I2CM_FM_SCL_CONFIG0				0xe4
#define I2CM_CONFIG0					0xe8
#define I2CM_CONTROL0					0xec
#define I2CM_STATUS0					0xf0
#define I2CM_INTERFACE_CONTROL0				0xf4
#define I2CM_ADDR					0xff000
#define I2CM_SLVADDR					0xfe0
#define I2CM_WR_MASK					0x1e
#define I2CM_EXT_READ					BIT(4)
#define I2CM_SHORT_READ					BIT(3)
#define I2CM_FM_READ					BIT(2)
#define I2CM_FM_WRITE					BIT(1)
#define I2CM_FM_EN					BIT(0)
#define I2CM_INTERFACE_CONTROL1				0xf8
#define I2CM_SEG_PTR					0x7f80
#define I2CM_SEG_ADDR					0x7f
#define I2CM_INTERFACE_WRDATA_0_3			0xfc
#define I2CM_INTERFACE_WRDATA_4_7			0x100
#define I2CM_INTERFACE_WRDATA_8_11			0x104
#define I2CM_INTERFACE_WRDATA_12_15			0x108
#define I2CM_INTERFACE_RDDATA_0_3			0x10c
#define I2CM_INTERFACE_RDDATA_4_7			0x110
#define I2CM_INTERFACE_RDDATA_8_11			0x114
#define I2CM_INTERFACE_RDDATA_12_15			0x118
/* SCDC Registers */
#define SCDC_CONFIG0					0x140
#define SCDC_I2C_FM_EN					BIT(12)
#define SCDC_UPD_FLAGS_AUTO_CLR				BIT(6)
#define SCDC_UPD_FLAGS_POLL_EN				BIT(4)
#define SCDC_CONTROL0					0x148
#define SCDC_STATUS0					0x150
#define STATUS_UPDATE					BIT(0)
#define FRL_START					BIT(4)
#define FLT_UPDATE					BIT(5)
/* FLT Registers */
#define FLT_CONFIG0					0x160
#define FLT_CONFIG1					0x164
#define FLT_CONFIG2					0x168
#define FLT_CONTROL0					0x170
/*  Main Unit 2 Registers */

Annotation

Implementation Notes