drivers/gpu/drm/display/drm_dp_tunnel.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/display/drm_dp_tunnel.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/display/drm_dp_tunnel.c
Extension
.c
Size
52471 bytes
Lines
1976
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct drm_dp_tunnel_regs {
	u8 buf[HWEIGHT64(DPTUN_INFO_REG_MASK)];
};

struct drm_dp_tunnel_group;

struct drm_dp_tunnel {
	struct drm_dp_tunnel_group *group;

	struct list_head node;

	struct kref kref;
	struct ref_tracker *tracker;
	struct drm_dp_aux *aux;
	char name[8];

	int bw_granularity;
	int estimated_bw;
	int allocated_bw;

	int max_dprx_rate;
	u8 max_dprx_lane_count;

	u8 adapter_id;

	bool bw_alloc_supported:1;
	bool bw_alloc_enabled:1;
	bool has_io_error:1;
	bool destroyed:1;
	bool pr_optimization_support:1;
};

struct drm_dp_tunnel_group_state;

struct drm_dp_tunnel_state {
	struct drm_dp_tunnel_group_state *group_state;

	struct drm_dp_tunnel_ref tunnel_ref;

	struct list_head node;

	u32 stream_mask;
	int *stream_bw;
};

struct drm_dp_tunnel_group_state {
	struct drm_private_state base;

	struct list_head tunnel_states;
};

struct drm_dp_tunnel_group {
	struct drm_private_obj base;
	struct drm_dp_tunnel_mgr *mgr;

	struct list_head tunnels;

	/* available BW including the allocated_bw of all tunnels in the group */
	int available_bw;

	u8 drv_group_id;
	char name[8];

	bool active:1;
};

struct drm_dp_tunnel_mgr {
	struct drm_device *dev;

	int group_count;
	struct drm_dp_tunnel_group *groups;
	wait_queue_head_t bw_req_queue;

#ifdef CONFIG_DRM_DISPLAY_DP_TUNNEL_STATE_DEBUG
	struct ref_tracker_dir ref_tracker;
#endif
};

/*
 * The following helpers provide a way to read out the tunneling DPCD
 * registers with a minimal amount of AUX transfers (1 transfer per contiguous
 * range, as permitted by the 16 byte per transfer AUX limit), not accessing
 * other registers to avoid any read side-effects.
 */
static int next_reg_area(int *offset)
{
	*offset = find_next_bit(dptun_info_regs, 64, *offset);

	return find_next_zero_bit(dptun_info_regs, 64, *offset + 1) - *offset;
}

Annotation

Implementation Notes