drivers/gpu/drm/display/drm_dsc_helper.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/display/drm_dsc_helper.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/display/drm_dsc_helper.c
Extension
.c
Size
50036 bytes
Lines
1567
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct rc_parameters {
	u16 initial_xmit_delay;
	u8 first_line_bpg_offset;
	u16 initial_offset;
	u8 flatness_min_qp;
	u8 flatness_max_qp;
	u8 rc_quant_incr_limit0;
	u8 rc_quant_incr_limit1;
	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};

struct rc_parameters_data {
	u8 bpp;
	u8 bpc;
	struct rc_parameters params;
};

#define DSC_BPP(bpp)	((bpp) << 4)

/*
 * Rate Control Related Parameter Recommended Values from DSC_v1.1 spec prior
 * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
 *
 * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
 */
static const struct rc_parameters_data rc_parameters_pre_scr[] = {
	{
		.bpp = DSC_BPP(6), .bpc = 8,
		{ 683, 15, 6144, 3, 13, 11, 11, {
			{ 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
			{ 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
			{ 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
			{ 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
			}
		}
	},
	{
		.bpp = DSC_BPP(8), .bpc = 8,
		{ 512, 12, 6144, 3, 12, 11, 11, {
			{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
			{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
			{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
			}
		}
	},
	{
		.bpp = DSC_BPP(8), .bpc = 10,
		{ 512, 12, 6144, 7, 16, 15, 15, {
			/*
			 * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
			 * VESA DSC 1.1 Table E-5 sets it to 4.
			 */
			{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
			{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
			{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
			}
		}
	},
	{
		.bpp = DSC_BPP(8), .bpc = 12,
		{ 512, 12, 6144, 11, 20, 19, 19, {
			{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
			{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
			{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
			{ 21, 23, -12 }
			}
		}
	},
	{
		.bpp = DSC_BPP(10), .bpc = 8,
		{ 410, 12, 5632, 3, 12, 11, 11, {
			{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
			{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
			{ 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
			}
		}
	},
	{
		.bpp = DSC_BPP(10), .bpc = 10,
		{ 410, 12, 5632, 7, 16, 15, 15, {
			{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
			{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
			{ 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
			}
		}

Annotation

Implementation Notes