drivers/gpu/drm/etnaviv/etnaviv_sched.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/etnaviv/etnaviv_sched.h

Extension

.h

Size

559 bytes

Lines

24

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• drm/gpu_scheduler.h

Detected Declarations

• struct etnaviv_gpu

Annotated Snippet

#ifndef __ETNAVIV_SCHED_H__
#define __ETNAVIV_SCHED_H__

#include <drm/gpu_scheduler.h>

struct etnaviv_gpu;

static inline
struct etnaviv_gem_submit *to_etnaviv_submit(struct drm_sched_job *sched_job)
{
	return container_of(sched_job, struct etnaviv_gem_submit, sched_job);
}

int etnaviv_sched_init(struct etnaviv_gpu *gpu);
void etnaviv_sched_fini(struct etnaviv_gpu *gpu);
int etnaviv_sched_push_job(struct etnaviv_gem_submit *submit);

#endif /* __ETNAVIV_SCHED_H__ */

Annotation

• Immediate include surface: `drm/gpu_scheduler.h`.
• Detected declarations: `struct etnaviv_gpu`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.