drivers/gpu/drm/exynos/regs-fimc.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/exynos/regs-fimc.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/exynos/regs-fimc.h
Extension
.h
Size
26249 bytes
Lines
666
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef EXYNOS_REGS_FIMC_H
#define EXYNOS_REGS_FIMC_H

/*
 * Register part
*/
/* Input source format */
#define EXYNOS_CISRCFMT		(0x00)
/* Window offset */
#define EXYNOS_CIWDOFST		(0x04)
/* Global control */
#define EXYNOS_CIGCTRL		(0x08)
/* Window offset 2 */
#define EXYNOS_CIWDOFST2	(0x14)
/* Y 1st frame start address for output DMA */
#define EXYNOS_CIOYSA1		(0x18)
/* Y 2nd frame start address for output DMA */
#define EXYNOS_CIOYSA2		(0x1c)
/* Y 3rd frame start address for output DMA */
#define EXYNOS_CIOYSA3		(0x20)
/* Y 4th frame start address for output DMA */
#define EXYNOS_CIOYSA4		(0x24)
/* Cb 1st frame start address for output DMA */
#define EXYNOS_CIOCBSA1		(0x28)
/* Cb 2nd frame start address for output DMA */
#define EXYNOS_CIOCBSA2		(0x2c)
/* Cb 3rd frame start address for output DMA */
#define EXYNOS_CIOCBSA3		(0x30)
/* Cb 4th frame start address for output DMA */
#define EXYNOS_CIOCBSA4		(0x34)
/* Cr 1st frame start address for output DMA */
#define EXYNOS_CIOCRSA1		(0x38)
/* Cr 2nd frame start address for output DMA */
#define EXYNOS_CIOCRSA2		(0x3c)
/* Cr 3rd frame start address for output DMA */
#define EXYNOS_CIOCRSA3		(0x40)
/* Cr 4th frame start address for output DMA */
#define EXYNOS_CIOCRSA4		(0x44)
/* Target image format */
#define EXYNOS_CITRGFMT		(0x48)
/* Output DMA control */
#define EXYNOS_CIOCTRL		(0x4c)
/* Pre-scaler control 1 */
#define EXYNOS_CISCPRERATIO	(0x50)
/* Pre-scaler control 2 */
#define EXYNOS_CISCPREDST		(0x54)
/* Main scaler control */
#define EXYNOS_CISCCTRL		(0x58)
/* Target area */
#define EXYNOS_CITAREA		(0x5c)
/* Status */
#define EXYNOS_CISTATUS		(0x64)
/* Status2 */
#define EXYNOS_CISTATUS2		(0x68)
/* Image capture enable command */
#define EXYNOS_CIIMGCPT		(0xc0)
/* Capture sequence */
#define EXYNOS_CICPTSEQ		(0xc4)
/* Image effects */
#define EXYNOS_CIIMGEFF		(0xd0)
/* Y frame start address for input DMA */
#define EXYNOS_CIIYSA0		(0xd4)
/* Cb frame start address for input DMA */
#define EXYNOS_CIICBSA0		(0xd8)
/* Cr frame start address for input DMA */
#define EXYNOS_CIICRSA0		(0xdc)
/* Input DMA Y Line Skip */
#define EXYNOS_CIILINESKIP_Y	(0xec)
/* Input DMA Cb Line Skip */
#define EXYNOS_CIILINESKIP_CB	(0xf0)
/* Input DMA Cr Line Skip */
#define EXYNOS_CIILINESKIP_CR	(0xf4)
/* Real input DMA image size */
#define EXYNOS_CIREAL_ISIZE	(0xf8)
/* Input DMA control */
#define EXYNOS_MSCTRL		(0xfc)
/* Y frame start address for input DMA */
#define EXYNOS_CIIYSA1		(0x144)
/* Cb frame start address for input DMA */
#define EXYNOS_CIICBSA1		(0x148)
/* Cr frame start address for input DMA */
#define EXYNOS_CIICRSA1		(0x14c)
/* Output DMA Y offset */
#define EXYNOS_CIOYOFF		(0x168)
/* Output DMA CB offset */
#define EXYNOS_CIOCBOFF		(0x16c)
/* Output DMA CR offset */
#define EXYNOS_CIOCROFF		(0x170)
/* Input DMA Y offset */
#define EXYNOS_CIIYOFF		(0x174)

Annotation

Implementation Notes