drivers/gpu/drm/exynos/regs-gsc.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/exynos/regs-gsc.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/exynos/regs-gsc.h- Extension
.h- Size
- 9899 bytes
- Lines
- 283
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef EXYNOS_REGS_GSC_H_
#define EXYNOS_REGS_GSC_H_
/* G-Scaler enable */
#define GSC_ENABLE 0x00
#define GSC_ENABLE_PP_UPDATE_TIME_MASK (1 << 9)
#define GSC_ENABLE_PP_UPDATE_TIME_CURR (0 << 9)
#define GSC_ENABLE_PP_UPDATE_TIME_EOPAS (1 << 9)
#define GSC_ENABLE_CLK_GATE_MODE_MASK (1 << 8)
#define GSC_ENABLE_CLK_GATE_MODE_FREE (1 << 8)
#define GSC_ENABLE_IPC_MODE_MASK (1 << 7)
#define GSC_ENABLE_NORM_MODE (0 << 7)
#define GSC_ENABLE_IPC_MODE (1 << 7)
#define GSC_ENABLE_PP_UPDATE_MODE_MASK (1 << 6)
#define GSC_ENABLE_PP_UPDATE_FIRE_MODE (1 << 6)
#define GSC_ENABLE_IN_PP_UPDATE (1 << 5)
#define GSC_ENABLE_ON_CLEAR_MASK (1 << 4)
#define GSC_ENABLE_ON_CLEAR_ONESHOT (1 << 4)
#define GSC_ENABLE_QOS_ENABLE (1 << 3)
#define GSC_ENABLE_OP_STATUS (1 << 2)
#define GSC_ENABLE_SFR_UPDATE (1 << 1)
#define GSC_ENABLE_ON (1 << 0)
/* G-Scaler S/W reset */
#define GSC_SW_RESET 0x04
#define GSC_SW_RESET_SRESET (1 << 0)
/* G-Scaler IRQ */
#define GSC_IRQ 0x08
#define GSC_IRQ_STATUS_OR_IRQ (1 << 17)
#define GSC_IRQ_STATUS_OR_FRM_DONE (1 << 16)
#define GSC_IRQ_OR_MASK (1 << 2)
#define GSC_IRQ_FRMDONE_MASK (1 << 1)
#define GSC_IRQ_ENABLE (1 << 0)
/* G-Scaler input control */
#define GSC_IN_CON 0x10
#define GSC_IN_CHROM_STRIDE_SEL_MASK (1 << 20)
#define GSC_IN_CHROM_STRIDE_SEPAR (1 << 20)
#define GSC_IN_RB_SWAP_MASK (1 << 19)
#define GSC_IN_RB_SWAP (1 << 19)
#define GSC_IN_ROT_MASK (7 << 16)
#define GSC_IN_ROT_270 (7 << 16)
#define GSC_IN_ROT_90_YFLIP (6 << 16)
#define GSC_IN_ROT_90_XFLIP (5 << 16)
#define GSC_IN_ROT_90 (4 << 16)
#define GSC_IN_ROT_180 (3 << 16)
#define GSC_IN_ROT_YFLIP (2 << 16)
#define GSC_IN_ROT_XFLIP (1 << 16)
#define GSC_IN_RGB_TYPE_MASK (3 << 14)
#define GSC_IN_RGB_HD_WIDE (3 << 14)
#define GSC_IN_RGB_HD_NARROW (2 << 14)
#define GSC_IN_RGB_SD_WIDE (1 << 14)
#define GSC_IN_RGB_SD_NARROW (0 << 14)
#define GSC_IN_YUV422_1P_ORDER_MASK (1 << 13)
#define GSC_IN_YUV422_1P_ORDER_LSB_Y (0 << 13)
#define GSC_IN_YUV422_1P_OEDER_LSB_C (1 << 13)
#define GSC_IN_CHROMA_ORDER_MASK (1 << 12)
#define GSC_IN_CHROMA_ORDER_CBCR (0 << 12)
#define GSC_IN_CHROMA_ORDER_CRCB (1 << 12)
#define GSC_IN_FORMAT_MASK (7 << 8)
#define GSC_IN_XRGB8888 (0 << 8)
#define GSC_IN_RGB565 (1 << 8)
#define GSC_IN_YUV420_2P (2 << 8)
#define GSC_IN_YUV420_3P (3 << 8)
#define GSC_IN_YUV422_1P (4 << 8)
#define GSC_IN_YUV422_2P (5 << 8)
#define GSC_IN_YUV422_3P (6 << 8)
#define GSC_IN_TILE_TYPE_MASK (1 << 4)
#define GSC_IN_TILE_C_16x8 (0 << 4)
#define GSC_IN_TILE_C_16x16 (1 << 4)
#define GSC_IN_TILE_MODE (1 << 3)
#define GSC_IN_LOCAL_SEL_MASK (3 << 1)
#define GSC_IN_LOCAL_CAM3 (3 << 1)
#define GSC_IN_LOCAL_FIMD_WB (2 << 1)
#define GSC_IN_LOCAL_CAM1 (1 << 1)
#define GSC_IN_LOCAL_CAM0 (0 << 1)
#define GSC_IN_PATH_MASK (1 << 0)
#define GSC_IN_PATH_LOCAL (1 << 0)
#define GSC_IN_PATH_MEMORY (0 << 0)
/* G-Scaler source image size */
#define GSC_SRCIMG_SIZE 0x14
#define GSC_SRCIMG_HEIGHT_MASK (0x1fff << 16)
#define GSC_SRCIMG_HEIGHT(x) ((x) << 16)
#define GSC_SRCIMG_WIDTH_MASK (0x3fff << 0)
#define GSC_SRCIMG_WIDTH(x) ((x) << 0)
/* G-Scaler source image offset */
#define GSC_SRCIMG_OFFSET 0x18
Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.