drivers/gpu/drm/gma500/psb_intel_drv.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/gma500/psb_intel_drv.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/gma500/psb_intel_drv.h- Extension
.h- Size
- 7266 bytes
- Lines
- 241
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/i2c.hlinux/i2c-algo-bit.hdrm/drm_crtc.hdrm/drm_encoder.hdrm/drm_probe_helper.hdrm/drm_vblank.hgma_display.h
Detected Declarations
struct psb_intel_mode_devicestruct gma_i2c_chanstruct gma_encoderstruct gma_connectorstruct psb_intel_crtc_statestruct gma_crtc
Annotated Snippet
struct psb_intel_mode_device {
/*
* Abstracted memory manager operations
*/
size_t(*bo_offset) (struct drm_device *dev, void *bo);
/*
* LVDS info
*/
int backlight_duty_cycle; /* restore backlight to this value */
bool panel_wants_dither;
struct drm_display_mode *panel_fixed_mode;
struct drm_display_mode *panel_fixed_mode2;
struct drm_display_mode *vbt_mode; /* if any */
uint32_t saveBLC_PWM_CTL;
};
struct gma_i2c_chan {
struct i2c_adapter base;
struct i2c_algo_bit_data algo;
u8 target_addr;
/* for getting at dev. private (mmio etc.) */
struct drm_device *drm_dev;
u32 reg; /* GPIO reg */
};
struct gma_encoder {
struct drm_encoder base;
int type;
bool needs_tv_clock;
void (*hot_plug)(struct gma_encoder *);
int crtc_mask;
int clone_mask;
u32 ddi_select; /* Channel info */
#define DDI0_SELECT 0x01
#define DDI1_SELECT 0x02
#define DP_MASK 0x8000
#define DDI_MASK 0x03
void *dev_priv; /* For sdvo_priv, lvds_priv, etc... */
/* FIXME: Either make SDVO and LVDS store it's i2c here or give CDV it's
own set of output privates */
struct gma_i2c_chan *i2c_bus;
};
struct gma_connector {
struct drm_connector base;
struct gma_encoder *encoder;
void (*save)(struct drm_connector *connector);
void (*restore)(struct drm_connector *connector);
};
struct psb_intel_crtc_state {
uint32_t saveDSPCNTR;
uint32_t savePIPECONF;
uint32_t savePIPESRC;
uint32_t saveDPLL;
uint32_t saveFP0;
uint32_t saveFP1;
uint32_t saveHTOTAL;
uint32_t saveHBLANK;
uint32_t saveHSYNC;
uint32_t saveVTOTAL;
uint32_t saveVBLANK;
uint32_t saveVSYNC;
uint32_t saveDSPSTRIDE;
uint32_t saveDSPSIZE;
uint32_t saveDSPPOS;
uint32_t saveDSPBASE;
uint32_t savePalette[256];
};
struct gma_crtc {
struct drm_crtc base;
int pipe;
int plane;
uint32_t cursor_addr;
struct psb_gem_object *cursor_pobj;
u8 lut_adj[256];
struct psb_intel_framebuffer *fbdev_fb;
/* a mode_set for fbdev users on this crtc */
struct drm_mode_set mode_set;
/* GEM object that holds our cursor */
struct drm_gem_object *cursor_obj;
Annotation
- Immediate include surface: `linux/i2c.h`, `linux/i2c-algo-bit.h`, `drm/drm_crtc.h`, `drm/drm_encoder.h`, `drm/drm_probe_helper.h`, `drm/drm_vblank.h`, `gma_display.h`.
- Detected declarations: `struct psb_intel_mode_device`, `struct gma_i2c_chan`, `struct gma_encoder`, `struct gma_connector`, `struct psb_intel_crtc_state`, `struct gma_crtc`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.