drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
Extension
.h
Size
24416 bytes
Lines
724
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct psb_intel_sdvo_caps {
    u8 vendor_id;
    u8 device_id;
    u8 device_rev_id;
    u8 sdvo_version_major;
    u8 sdvo_version_minor;
    unsigned int sdvo_inputs_mask:2;
    unsigned int smooth_scaling:1;
    unsigned int sharp_scaling:1;
    unsigned int up_scaling:1;
    unsigned int down_scaling:1;
    unsigned int stall_support:1;
    unsigned int pad:1;
    u16 output_flags;
} __attribute__((packed));

/** This matches the EDID DTD structure, more or less */
struct psb_intel_sdvo_dtd {
    struct {
	u16 clock;		/**< pixel clock, in 10kHz units */
	u8 h_active;		/**< lower 8 bits (pixels) */
	u8 h_blank;		/**< lower 8 bits (pixels) */
	u8 h_high;		/**< upper 4 bits each h_active, h_blank */
	u8 v_active;		/**< lower 8 bits (lines) */
	u8 v_blank;		/**< lower 8 bits (lines) */
	u8 v_high;		/**< upper 4 bits each v_active, v_blank */
    } part1;

    struct {
	u8 h_sync_off;	/**< lower 8 bits, from hblank start */
	u8 h_sync_width;	/**< lower 8 bits (pixels) */
	/** lower 4 bits each vsync offset, vsync width */
	u8 v_sync_off_width;
	/**
	 * 2 high bits of hsync offset, 2 high bits of hsync width,
	 * bits 4-5 of vsync offset, and 2 high bits of vsync width.
	 */
	u8 sync_off_width_high;
	u8 dtd_flags;
	u8 sdvo_flags;
	/** bits 6-7 of vsync offset at bits 6-7 */
	u8 v_sync_off_high;
	u8 reserved;
    } part2;
} __attribute__((packed));

struct psb_intel_sdvo_pixel_clock_range {
    u16 min;			/**< pixel clock, in 10kHz units */
    u16 max;			/**< pixel clock, in 10kHz units */
} __attribute__((packed));

struct psb_intel_sdvo_preferred_input_timing_args {
    u16 clock;
    u16 width;
    u16 height;
    u8	interlace:1;
    u8	scaled:1;
    u8	pad:6;
} __attribute__((packed));

/* I2C registers for SDVO */
#define SDVO_I2C_ARG_0				0x07
#define SDVO_I2C_ARG_1				0x06
#define SDVO_I2C_ARG_2				0x05
#define SDVO_I2C_ARG_3				0x04
#define SDVO_I2C_ARG_4				0x03
#define SDVO_I2C_ARG_5				0x02
#define SDVO_I2C_ARG_6				0x01
#define SDVO_I2C_ARG_7				0x00
#define SDVO_I2C_OPCODE				0x08
#define SDVO_I2C_CMD_STATUS			0x09
#define SDVO_I2C_RETURN_0			0x0a
#define SDVO_I2C_RETURN_1			0x0b
#define SDVO_I2C_RETURN_2			0x0c
#define SDVO_I2C_RETURN_3			0x0d
#define SDVO_I2C_RETURN_4			0x0e
#define SDVO_I2C_RETURN_5			0x0f
#define SDVO_I2C_RETURN_6			0x10
#define SDVO_I2C_RETURN_7			0x11
#define SDVO_I2C_VENDOR_BEGIN			0x20

/* Status results */
#define SDVO_CMD_STATUS_POWER_ON		0x0
#define SDVO_CMD_STATUS_SUCCESS			0x1
#define SDVO_CMD_STATUS_NOTSUPP			0x2
#define SDVO_CMD_STATUS_INVALID_ARG		0x3
#define SDVO_CMD_STATUS_PENDING			0x4
#define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED	0x5
#define SDVO_CMD_STATUS_SCALING_NOT_SUPP	0x6

Annotation

Implementation Notes