drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
Extension
.h
Size
6541 bytes
Lines
205
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef HIBMC_DRM_HW_H
#define HIBMC_DRM_HW_H

/* register definition */
#define HIBMC_MISC_CTRL				0x4

#define HIBMC_MSCCTL_LOCALMEM_RESET(x)		((x) << 6)
#define HIBMC_MSCCTL_LOCALMEM_RESET_MASK	0x40

#define HIBMC_CURRENT_GATE			0x000040
#define HIBMC_CURR_GATE_DISPLAY(x)		((x) << 2)
#define HIBMC_CURR_GATE_DISPLAY_MASK		0x4

#define HIBMC_CURR_GATE_LOCALMEM(x)		((x) << 1)
#define HIBMC_CURR_GATE_LOCALMEM_MASK		0x2

#define HIBMC_MODE0_GATE			0x000044
#define HIBMC_MODE1_GATE			0x000048
#define HIBMC_POWER_MODE_CTRL			0x00004C

#define HIBMC_PW_MODE_CTL_OSC_INPUT(x)		((x) << 3)
#define HIBMC_PW_MODE_CTL_OSC_INPUT_MASK	0x8

#define HIBMC_PW_MODE_CTL_MODE(x)		((x) << 0)
#define HIBMC_PW_MODE_CTL_MODE_MASK		0x03
#define HIBMC_PW_MODE_CTL_MODE_SHIFT		0

#define HIBMC_PW_MODE_CTL_MODE_MODE0		0
#define HIBMC_PW_MODE_CTL_MODE_MODE1		1
#define HIBMC_PW_MODE_CTL_MODE_SLEEP		2

#define HIBMC_PANEL_PLL_CTRL			0x00005C
#define HIBMC_CRT_PLL_CTRL			0x000060

#define HIBMC_PLL_CTRL_BYPASS(x)		((x) << 18)
#define HIBMC_PLL_CTRL_BYPASS_MASK		0x40000

#define HIBMC_PLL_CTRL_POWER(x)			((x) << 17)
#define HIBMC_PLL_CTRL_POWER_MASK		0x20000

#define HIBMC_PLL_CTRL_INPUT(x)			((x) << 16)
#define HIBMC_PLL_CTRL_INPUT_MASK		0x10000

#define HIBMC_PLL_CTRL_POD(x)			((x) << 14)
#define HIBMC_PLL_CTRL_POD_MASK			0xC000

#define HIBMC_PLL_CTRL_OD(x)			((x) << 12)
#define HIBMC_PLL_CTRL_OD_MASK			0x3000

#define HIBMC_PLL_CTRL_N(x)			((x) << 8)
#define HIBMC_PLL_CTRL_N_MASK			0xF00

#define HIBMC_PLL_CTRL_M(x)			((x) << 0)
#define HIBMC_PLL_CTRL_M_MASK			0xFF

#define HIBMC_CRT_DISP_CTL			0x80200

#define HIBMC_CRT_DISP_CTL_DPMS(x)		((x) << 30)
#define HIBMC_CRT_DISP_CTL_DPMS_MASK		0xc0000000

#define HIBMC_CRT_DPMS_ON			0
#define HIBMC_CRT_DPMS_OFF			3

#define HIBMC_CRT_DISP_CTL_CRTSELECT(x)		((x) << 25)
#define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK	0x2000000

#define HIBMC_CRTSELECT_CRT			1

#define HIBMC_CRT_DISP_CTL_CLOCK_PHASE(x)	((x) << 14)
#define HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK	0x4000

#define HIBMC_CRT_DISP_CTL_VSYNC_PHASE(x)	((x) << 13)
#define HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK	0x2000

#define HIBMC_CRT_DISP_CTL_HSYNC_PHASE(x)	((x) << 12)
#define HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK	0x1000

#define HIBMC_CRT_DISP_CTL_TIMING(x)		((x) << 8)
#define HIBMC_CRT_DISP_CTL_TIMING_MASK		0x100

#define HIBMC_CTL_DISP_CTL_GAMMA(x)		((x) << 3)
#define HIBMC_CTL_DISP_CTL_GAMMA_MASK		0x08

#define HIBMC_CRT_DISP_CTL_PLANE(x)		((x) << 2)
#define HIBMC_CRT_DISP_CTL_PLANE_MASK		4

#define HIBMC_CRT_DISP_CTL_FORMAT(x)		((x) << 0)
#define HIBMC_CRT_DISP_CTL_FORMAT_MASK		0x03

#define HIBMC_CRT_FB_ADDRESS			0x080204

Annotation

Implementation Notes