drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
Extension
.h
Size
10722 bytes
Lines
274
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __BXT_DPIO_PHY_REGS_H__
#define __BXT_DPIO_PHY_REGS_H__

#include "intel_display_reg_defs.h"

/* BXT PHY registers */
#define _BXT_PHY0_BASE			0x6C000
#define _BXT_PHY1_BASE			0x162000
#define _BXT_PHY2_BASE			0x163000
#define BXT_PHY_BASE(phy) \
	 _PICK_EVEN_2RANGES(phy, 1, \
			    _BXT_PHY0_BASE, _BXT_PHY0_BASE, \
			    _BXT_PHY1_BASE, _BXT_PHY2_BASE)

#define _BXT_PHY(phy, reg) \
	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))

#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
	(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
					 (reg_ch1) - _BXT_PHY0_BASE))
#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
#define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 + \
					  ((lane) & 1) * 0x80)
#define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \
	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))

/* BXT PHY PLL registers */
#define _PORT_PLL_A			0x46074
#define _PORT_PLL_B			0x46078
#define _PORT_PLL_C			0x4607c
#define   PORT_PLL_ENABLE		REG_BIT(31)
#define   PORT_PLL_LOCK			REG_BIT(30)
#define   PORT_PLL_REF_SEL		REG_BIT(27)
#define   PORT_PLL_POWER_ENABLE		REG_BIT(26)
#define   PORT_PLL_POWER_STATE		REG_BIT(25)
#define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)

#define _PORT_PLL_EBB_0_A		0x162034
#define _PORT_PLL_EBB_0_B		0x6C034
#define _PORT_PLL_EBB_0_C		0x6C340
#define   PORT_PLL_P1_MASK		REG_GENMASK(15, 13)
#define   PORT_PLL_P1(p1)		REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
#define   PORT_PLL_P2_MASK		REG_GENMASK(12, 8)
#define   PORT_PLL_P2(p2)		REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
#define BXT_PORT_PLL_EBB_0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PLL_EBB_0_B, \
							 _PORT_PLL_EBB_0_C)

#define _PORT_PLL_EBB_4_A		0x162038
#define _PORT_PLL_EBB_4_B		0x6C038
#define _PORT_PLL_EBB_4_C		0x6C344
#define   PORT_PLL_RECALIBRATE		REG_BIT(14)
#define   PORT_PLL_10BIT_CLK_ENABLE	REG_BIT(13)
#define BXT_PORT_PLL_EBB_4(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PLL_EBB_4_B, \
							 _PORT_PLL_EBB_4_C)

#define _PORT_PLL_0_A			0x162100
#define _PORT_PLL_0_B			0x6C100
#define _PORT_PLL_0_C			0x6C380
/* PORT_PLL_0_A */
#define   PORT_PLL_M2_INT_MASK		REG_GENMASK(7, 0)
#define   PORT_PLL_M2_INT(m2_int)	REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
/* PORT_PLL_1_A */
#define   PORT_PLL_N_MASK		REG_GENMASK(11, 8)
#define   PORT_PLL_N(n)			REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
/* PORT_PLL_2_A */
#define   PORT_PLL_M2_FRAC_MASK		REG_GENMASK(21, 0)
#define   PORT_PLL_M2_FRAC(m2_frac)	REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
/* PORT_PLL_3_A */
#define   PORT_PLL_M2_FRAC_ENABLE	REG_BIT(16)
/* PORT_PLL_6_A */
#define   PORT_PLL_GAIN_CTL_MASK	REG_GENMASK(18, 16)
#define   PORT_PLL_GAIN_CTL(x)		REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
#define   PORT_PLL_INT_COEFF_MASK	REG_GENMASK(12, 8)
#define   PORT_PLL_INT_COEFF(x)		REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
#define   PORT_PLL_PROP_COEFF_MASK	REG_GENMASK(3, 0)
#define   PORT_PLL_PROP_COEFF(x)	REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
/* PORT_PLL_8_A */
#define   PORT_PLL_TARGET_CNT_MASK	REG_GENMASK(9, 0)
#define   PORT_PLL_TARGET_CNT(x)	REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
/* PORT_PLL_9_A */
#define  PORT_PLL_LOCK_THRESHOLD_MASK	REG_GENMASK(3, 1)
#define  PORT_PLL_LOCK_THRESHOLD(x)	REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
/* PORT_PLL_10_A */
#define  PORT_PLL_DCO_AMP_OVR_EN_H	REG_BIT(27)
#define  PORT_PLL_DCO_AMP_MASK		REG_GENMASK(13, 10)
#define  PORT_PLL_DCO_AMP(x)		REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
#define _PORT_PLL_BASE(phy, ch)		_BXT_PHY_CH(phy, ch, \

Annotation

Implementation Notes