drivers/gpu/drm/i915/display/hsw_ips.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/hsw_ips.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/hsw_ips.c
Extension
.c
Size
9895 bytes
Lines
375
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2022 Intel Corporation
 */

#include <linux/debugfs.h>

#include <drm/drm_print.h>
#include <drm/intel/intel_pcode_regs.h>

#include "hsw_ips.h"
#include "intel_color_regs.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_parent.h"

static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
{
	struct intel_display *display = to_intel_display(crtc_state);
	u32 val;

	if (!crtc_state->ips_enabled)
		return;

	/*
	 * We can only enable IPS after we enable a plane and wait for a vblank
	 * This function is called from post_plane_update, which is run after
	 * a vblank wait.
	 */
	drm_WARN_ON(display->drm,
		    !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));

	val = IPS_ENABLE;

	if (display->ips.false_color)
		val |= IPS_FALSE_COLOR;

	if (display->platform.broadwell) {
		drm_WARN_ON(display->drm,
			    intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL,
						     val | IPS_PCODE_CONTROL));
		/*
		 * Quoting Art Runyan: "its not safe to expect any particular
		 * value in IPS_CTL bit 31 after enabling IPS through the
		 * mailbox." Moreover, the mailbox may return a bogus state,
		 * so we need to just enable it and continue on.
		 */
	} else {
		intel_de_write(display, IPS_CTL, val);
		/*
		 * The bit only becomes 1 in the next vblank, so this wait here
		 * is essentially intel_wait_for_vblank. If we don't have this
		 * and don't wait for vblanks until the end of crtc_enable, then
		 * the HW state readout code will complain that the expected
		 * IPS_CTL value is not the one we read.
		 */
		if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE, 50))
			drm_err(display->drm,
				"Timed out waiting for IPS enable\n");
	}
}

bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
{
	struct intel_display *display = to_intel_display(crtc_state);
	bool need_vblank_wait = false;

	if (!crtc_state->ips_enabled)
		return need_vblank_wait;

	if (display->platform.broadwell) {
		drm_WARN_ON(display->drm,
			    intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL, 0));
		/*
		 * Wait for PCODE to finish disabling IPS. The BSpec specified
		 * 42ms timeout value leads to occasional timeouts so use 100ms
		 * instead.
		 */
		if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE, 100))
			drm_err(display->drm,
				"Timed out waiting for IPS disable\n");
	} else {
		intel_de_write(display, IPS_CTL, 0);
		intel_de_posting_read(display, IPS_CTL);
	}

	/* We need to wait for a vblank before we can disable the plane. */
	need_vblank_wait = true;

Annotation

Implementation Notes