drivers/gpu/drm/i915/display/icl_dsi_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/icl_dsi_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/icl_dsi_regs.h
Extension
.h
Size
12401 bytes
Lines
345
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ICL_DSI_REGS_H__
#define __ICL_DSI_REGS_H__

#include "intel_display_reg_defs.h"

/* Gen11 DSI */
#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
						    dsi0, dsi1)
#define _ICL_DSI_ESC_CLK_DIV0		0x6b090
#define _ICL_DSI_ESC_CLK_DIV1		0x6b890
#define ICL_DSI_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
							_ICL_DSI_ESC_CLK_DIV0, \
							_ICL_DSI_ESC_CLK_DIV1)
#define _ICL_DPHY_ESC_CLK_DIV0		0x162190
#define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
#define ICL_DPHY_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
						_ICL_DPHY_ESC_CLK_DIV0, \
						_ICL_DPHY_ESC_CLK_DIV1)
#define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
#define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16
#define  ICL_ESC_CLK_DIV_MASK			0x1ff
#define  ICL_ESC_CLK_DIV_SHIFT			0
#define DSI_MAX_ESC_CLK			20000		/* in KHz */

#define _ADL_MIPIO_REG			0x180
#define ADL_MIPIO_DW(port, dw)		_MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))
#define   TX_ESC_CLK_DIV_PHY_SEL	REGBIT(16)
#define   TX_ESC_CLK_DIV_PHY_MASK	REG_GENMASK(23, 16)
#define   TX_ESC_CLK_DIV_PHY		REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)

#define _DSI_CMD_FRMCTL_0		0x6b034
#define _DSI_CMD_FRMCTL_1		0x6b834
#define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
						   _DSI_CMD_FRMCTL_0,\
						   _DSI_CMD_FRMCTL_1)
#define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
#define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
#define   DSI_NULL_PACKET_ENABLE		(1 << 28)
#define   DSI_FRAME_IN_PROGRESS			(1 << 0)

#define _DSI_INTR_MASK_REG_0		0x6b070
#define _DSI_INTR_MASK_REG_1		0x6b870
#define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
						   _DSI_INTR_MASK_REG_0,\
						   _DSI_INTR_MASK_REG_1)

#define _DSI_INTR_IDENT_REG_0		0x6b074
#define _DSI_INTR_IDENT_REG_1		0x6b874
#define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
						   _DSI_INTR_IDENT_REG_0,\
						   _DSI_INTR_IDENT_REG_1)
#define   DSI_TE_EVENT				(1 << 31)
#define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
#define   DSI_TX_DATA				(1 << 29)
#define   DSI_ULPS_ENTRY_DONE			(1 << 28)
#define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
#define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
#define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
#define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
#define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
#define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
#define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
#define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
#define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
#define   DSI_FRAME_UPDATE_DONE			(1 << 16)
#define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
#define   DSI_INVALID_TX_LENGTH			(1 << 13)
#define   DSI_INVALID_VC			(1 << 12)
#define   DSI_INVALID_DATA_TYPE			(1 << 11)
#define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
#define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
#define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
#define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
#define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
#define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
#define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
#define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
#define   DSI_EOT_SYNC_ERROR			(1 << 2)
#define   DSI_SOT_SYNC_ERROR			(1 << 1)
#define   DSI_SOT_ERROR				(1 << 0)

/* ICL DSI MODE control */
#define _ICL_DSI_IO_MODECTL_0				0x6B094
#define _ICL_DSI_IO_MODECTL_1				0x6B894
#define ICL_DSI_IO_MODECTL(port)	_MMIO_PORT(port,	\
						    _ICL_DSI_IO_MODECTL_0, \
						    _ICL_DSI_IO_MODECTL_1)
#define  COMBO_PHY_MODE_DSI				(1 << 0)

/* TGL DSI Chicken register */

Annotation

Implementation Notes