drivers/gpu/drm/i915/display/intel_cdclk.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_cdclk.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_cdclk.c
Extension
.c
Size
126447 bytes
Lines
4262
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct intel_cdclk_state {
	struct intel_global_state base;

	/*
	 * Logical configuration of cdclk (used for all scaling,
	 * watermark, etc. calculations and checks). This is
	 * computed as if all enabled crtcs were active.
	 */
	struct intel_cdclk_config logical;

	/*
	 * Actual configuration of cdclk, can be different from the
	 * logical configuration only when all crtc's are DPMS off.
	 */
	struct intel_cdclk_config actual;

	/* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */
	int dbuf_bw_min_cdclk;
	/* minimum acceptable cdclk for each pipe */
	int min_cdclk[I915_MAX_PIPES];
	/* minimum acceptable voltage level for each pipe */
	u8 min_voltage_level[I915_MAX_PIPES];

	/* pipe to which cd2x update is synchronized */
	enum pipe pipe;

	/* forced minimum cdclk for glk+ audio w/a */
	int force_min_cdclk;

	/* bitmask of enabled pipes */
	u8 enabled_pipes;

	/* bitmask of active pipes */
	u8 active_pipes;

	/* update cdclk with pipes disabled */
	bool disable_pipes;
};

struct intel_cdclk_funcs {
	void (*get_cdclk)(struct intel_display *display,
			  struct intel_cdclk_config *cdclk_config);
	void (*set_cdclk)(struct intel_display *display,
			  const struct intel_cdclk_config *cdclk_config,
			  enum pipe pipe);
	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
	u8 (*calc_voltage_level)(int cdclk);
};

void intel_cdclk_get_cdclk(struct intel_display *display,
			   struct intel_cdclk_config *cdclk_config)
{
	display->cdclk.funcs->get_cdclk(display, cdclk_config);
}

static void intel_cdclk_set_cdclk(struct intel_display *display,
				  const struct intel_cdclk_config *cdclk_config,
				  enum pipe pipe)
{
	display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe);
}

static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
{
	struct intel_display *display = to_intel_display(state);

	return display->cdclk.funcs->modeset_calc_cdclk(state);
}

static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
					 int cdclk)
{
	return display->cdclk.funcs->calc_voltage_level(cdclk);
}

static void fixed_133mhz_get_cdclk(struct intel_display *display,
				   struct intel_cdclk_config *cdclk_config)
{
	cdclk_config->cdclk = 133333;
}

static void fixed_200mhz_get_cdclk(struct intel_display *display,
				   struct intel_cdclk_config *cdclk_config)
{
	cdclk_config->cdclk = 200000;
}

static void fixed_266mhz_get_cdclk(struct intel_display *display,
				   struct intel_cdclk_config *cdclk_config)
{

Annotation

Implementation Notes