drivers/gpu/drm/i915/display/intel_color.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_color.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_color.c
Extension
.c
Size
129252 bytes
Lines
4390
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct intel_color_funcs {
	int (*color_check)(struct intel_atomic_state *state,
			   struct intel_crtc *crtc);
	/*
	 * Program non-arming double buffered color management registers
	 * before vblank evasion. The registers should then latch after
	 * the arming register is written (by color_commit_arm()) during
	 * the next vblank start, alongside any other double buffered
	 * registers involved with the same commit. This hook is optional.
	 */
	void (*color_commit_noarm)(struct intel_dsb *dsb,
				   const struct intel_crtc_state *crtc_state);
	/*
	 * Program arming double buffered color management registers
	 * during vblank evasion. The registers (and whatever other registers
	 * they arm that were written by color_commit_noarm) should then latch
	 * during the next vblank start, alongside any other double buffered
	 * registers involved with the same commit.
	 */
	void (*color_commit_arm)(struct intel_dsb *dsb,
				 const struct intel_crtc_state *crtc_state);
	/*
	 * Perform any extra tasks needed after all the
	 * double buffered registers have been latched.
	 */
	void (*color_post_update)(const struct intel_crtc_state *crtc_state);
	/*
	 * Load LUTs (and other single buffered color management
	 * registers). Will (hopefully) be called during the vblank
	 * following the latching of any double buffered registers
	 * involved with the same commit.
	 */
	void (*load_luts)(const struct intel_crtc_state *crtc_state);
	/*
	 * Read out the LUTs from the hardware into the software state.
	 * Used by eg. the hardware state checker.
	 */
	void (*read_luts)(struct intel_crtc_state *crtc_state);
	/*
	 * Compare the LUTs
	 */
	bool (*lut_equal)(const struct intel_crtc_state *crtc_state,
			  const struct drm_property_blob *blob1,
			  const struct drm_property_blob *blob2,
			  bool is_pre_csc_lut);
	/*
	 * Read out the CSCs (if any) from the hardware into the
	 * software state. Used by eg. the hardware state checker.
	 */
	void (*read_csc)(struct intel_crtc_state *crtc_state);
	/*
	 * Read config other than LUTs and CSCs, before them. Optional.
	 */
	void (*get_config)(struct intel_crtc_state *crtc_state);

	/* Plane CSC*/
	void (*load_plane_csc_matrix)(struct intel_dsb *dsb,
				      const struct intel_plane_state *plane_state);

	/* Plane Pre/Post CSC */
	void (*load_plane_luts)(struct intel_dsb *dsb,
				const struct intel_plane_state *plane_state);
};

#define CTM_COEFF_SIGN	(1ULL << 63)

#define CTM_COEFF_1_0	(1ULL << 32)
#define CTM_COEFF_2_0	(CTM_COEFF_1_0 << 1)
#define CTM_COEFF_4_0	(CTM_COEFF_2_0 << 1)
#define CTM_COEFF_8_0	(CTM_COEFF_4_0 << 1)
#define CTM_COEFF_0_5	(CTM_COEFF_1_0 >> 1)
#define CTM_COEFF_0_25	(CTM_COEFF_0_5 >> 1)
#define CTM_COEFF_0_125	(CTM_COEFF_0_25 >> 1)

#define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)

#define CTM_COEFF_NEGATIVE(coeff)	(((coeff) & CTM_COEFF_SIGN) != 0)
#define CTM_COEFF_ABS(coeff)		((coeff) & (CTM_COEFF_SIGN - 1))

#define LEGACY_LUT_LENGTH		256

/*
 * ILK+ csc matrix:
 *
 * |R/Cr|   | c0 c1 c2 |   ( |R/Cr|   |preoff0| )   |postoff0|
 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
 * |B/Cb|   | c6 c7 c8 |   ( |B/Cb|   |preoff2| )   |postoff2|
 *
 * ILK/SNB don't have explicit post offsets, and instead
 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:

Annotation

Implementation Notes