drivers/gpu/drm/i915/display/intel_color_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_color_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_color_regs.h
Extension
.h
Size
16672 bytes
Lines
349
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INTEL_COLOR_REGS_H__
#define __INTEL_COLOR_REGS_H__

#include "intel_display_reg_defs.h"

/* GMCH palette */
#define _PALETTE_A		0xa000
#define _PALETTE_B		0xa800
#define _CHV_PALETTE_C		0xc000
/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
#define   PALETTE_RED_MASK		REG_GENMASK(23, 16)
#define   PALETTE_GREEN_MASK		REG_GENMASK(15, 8)
#define   PALETTE_BLUE_MASK		REG_GENMASK(7, 0)
/* pre-i965 10bit interpolated mode ldw */
#define   PALETTE_10BIT_RED_LDW_MASK	REG_GENMASK(23, 16)
#define   PALETTE_10BIT_GREEN_LDW_MASK	REG_GENMASK(15, 8)
#define   PALETTE_10BIT_BLUE_LDW_MASK	REG_GENMASK(7, 0)
/* pre-i965 10bit interpolated mode udw */
#define   PALETTE_10BIT_RED_EXP_MASK	REG_GENMASK(23, 22)
#define   PALETTE_10BIT_RED_MANT_MASK	REG_GENMASK(21, 18)
#define   PALETTE_10BIT_RED_UDW_MASK	REG_GENMASK(17, 16)
#define   PALETTE_10BIT_GREEN_EXP_MASK	REG_GENMASK(15, 14)
#define   PALETTE_10BIT_GREEN_MANT_MASK	REG_GENMASK(13, 10)
#define   PALETTE_10BIT_GREEN_UDW_MASK	REG_GENMASK(9, 8)
#define   PALETTE_10BIT_BLUE_EXP_MASK	REG_GENMASK(7, 6)
#define   PALETTE_10BIT_BLUE_MANT_MASK	REG_GENMASK(5, 2)
#define   PALETTE_10BIT_BLUE_UDW_MASK	REG_GENMASK(1, 0)
#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +			\
			       _PICK_EVEN_2RANGES(pipe, 2,			\
						  _PALETTE_A, _PALETTE_B,	\
						  _CHV_PALETTE_C, _CHV_PALETTE_C) + \
						  (i) * 4)

/* i965/g4x/vlv/chv */
#define  _PIPEAGCMAX			0x70010
#define  _PIPEBGCMAX			0x71010
#define PIPEGCMAX(dev_priv, pipe, i)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */

/* ilk+ palette */
#define _LGC_PALETTE_A           0x4a000
#define _LGC_PALETTE_B           0x4a800
/* see PALETTE_* for the bits */
#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)

/* ilk/snb precision palette */
#define _PREC_PALETTE_A           0x4b000
#define _PREC_PALETTE_B           0x4c000
/* 10bit mode */
#define   PREC_PALETTE_10_RED_MASK		REG_GENMASK(29, 20)
#define   PREC_PALETTE_10_GREEN_MASK		REG_GENMASK(19, 10)
#define   PREC_PALETTE_10_BLUE_MASK		REG_GENMASK(9, 0)
/* 12.4 interpolated mode ldw */
#define   PREC_PALETTE_12P4_RED_LDW_MASK	REG_GENMASK(29, 24)
#define   PREC_PALETTE_12P4_GREEN_LDW_MASK	REG_GENMASK(19, 14)
#define   PREC_PALETTE_12P4_BLUE_LDW_MASK	REG_GENMASK(9, 4)
/* 12.4 interpolated mode udw */
#define   PREC_PALETTE_12P4_RED_UDW_MASK	REG_GENMASK(29, 20)
#define   PREC_PALETTE_12P4_GREEN_UDW_MASK	REG_GENMASK(19, 10)
#define   PREC_PALETTE_12P4_BLUE_UDW_MASK	REG_GENMASK(9, 0)
#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)

#define  _PREC_PIPEAGCMAX              0x4d000
#define  _PREC_PIPEBGCMAX              0x4d010
#define PREC_PIPEGCMAX(pipe, i)        _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */

#define _GAMMA_MODE_A		0x4a480
#define _GAMMA_MODE_B		0x4ac80
#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
#define  PRE_CSC_GAMMA_ENABLE			REG_BIT(31) /* icl+ */
#define  POST_CSC_GAMMA_ENABLE			REG_BIT(30) /* icl+ */
#define  PALETTE_ANTICOL_DISABLE		REG_BIT(15) /* skl+ */
#define  GAMMA_MODE_MODE_MASK			REG_GENMASK(1, 0)
#define  GAMMA_MODE_MODE_8BIT			REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0)
#define  GAMMA_MODE_MODE_10BIT			REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1)
#define  GAMMA_MODE_MODE_12BIT			REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2)
#define  GAMMA_MODE_MODE_SPLIT			REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */
#define  GAMMA_MODE_MODE_12BIT_MULTI_SEG	REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */

/* pipe CSC */
#define _PIPE_A_CSC_COEFF_RY_GY	0x49010
#define _PIPE_A_CSC_COEFF_BY	0x49014
#define _PIPE_A_CSC_COEFF_RU_GU	0x49018
#define _PIPE_A_CSC_COEFF_BU	0x4901c
#define _PIPE_A_CSC_COEFF_RV_GV	0x49020
#define _PIPE_A_CSC_COEFF_BV	0x49024

#define _PIPE_A_CSC_MODE	0x49028
#define  ICL_CSC_ENABLE			(1 << 31) /* icl+ */
#define  ICL_OUTPUT_CSC_ENABLE		(1 << 30) /* icl+ */
#define  CSC_BLACK_SCREEN_OFFSET	(1 << 2) /* ilk/snb */

Annotation

Implementation Notes