drivers/gpu/drm/i915/display/intel_cx0_phy.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_cx0_phy.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_cx0_phy.c
Extension
.c
Size
116318 bytes
Lines
3860
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct intel_cx0pll_params {
	const char *name;
	bool is_c10;
	bool is_hdmi;
	int clock_rate;
	union {
		const struct intel_c10pll_state *c10;
		const struct intel_c20pll_state *c20;
	};
};

#define __C10PLL_PARAMS(__is_hdmi, __clock_rate, __state) { \
	.name = __stringify(__state), \
	.is_c10 = true, \
	.is_hdmi = __is_hdmi, \
	.clock_rate = __clock_rate, \
	.c10 = &__state, \
}

#define __C20PLL_PARAMS(__is_hdmi, __clock_rate, __state)    { \
	.name = __stringify(__state), \
	.is_c10 = false, \
	.is_hdmi = __is_hdmi, \
	.clock_rate = __clock_rate, \
	.c20 = &__state, \
}

#define C10PLL_HDMI_PARAMS(__clock_rate, __state)       __C10PLL_PARAMS(true, __clock_rate, __state)
#define C10PLL_DP_PARAMS(__clock_rate, __state)         __C10PLL_PARAMS(false, __clock_rate, __state)

#define C20PLL_HDMI_PARAMS(__clock_rate, __state)       __C20PLL_PARAMS(true, __clock_rate, __state)
#define C20PLL_DP_PARAMS(__clock_rate, __state)         __C20PLL_PARAMS(false, __clock_rate, __state)

static const struct intel_cx0pll_params mtl_c10_dp_tables[] = {
	C10PLL_DP_PARAMS(162000, mtl_c10_dp_rbr),
	C10PLL_DP_PARAMS(270000, mtl_c10_dp_hbr1),
	C10PLL_DP_PARAMS(540000, mtl_c10_dp_hbr2),
	C10PLL_DP_PARAMS(810000, mtl_c10_dp_hbr3),
	{}
};

static const struct intel_cx0pll_params mtl_c10_edp_tables[] = {
	C10PLL_DP_PARAMS(162000, mtl_c10_dp_rbr),
	C10PLL_DP_PARAMS(216000, mtl_c10_edp_r216),
	C10PLL_DP_PARAMS(243000, mtl_c10_edp_r243),
	C10PLL_DP_PARAMS(270000, mtl_c10_dp_hbr1),
	C10PLL_DP_PARAMS(324000, mtl_c10_edp_r324),
	C10PLL_DP_PARAMS(432000, mtl_c10_edp_r432),
	C10PLL_DP_PARAMS(540000, mtl_c10_dp_hbr2),
	C10PLL_DP_PARAMS(675000, mtl_c10_edp_r675),
	C10PLL_DP_PARAMS(810000, mtl_c10_dp_hbr3),
	{}
};

/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
	.tx = {	0xbe88, /* tx cfg0 */
		0x5800, /* tx cfg1 */
		0x0000, /* tx cfg2 */
		},
	.cmn = {0x0500, /* cmn cfg0*/
		0x0005, /* cmn cfg1 */
		0x0000, /* cmn cfg2 */
		0x0000, /* cmn cfg3 */
		},
	.mpllb = { 0x50a8,	/* mpllb cfg0 */
		0x2120,		/* mpllb cfg1 */
		0xcd9a,		/* mpllb cfg2 */
		0xbfc1,		/* mpllb cfg3 */
		0x5ab8,         /* mpllb cfg4 */
		0x4c34,         /* mpllb cfg5 */
		0x2000,		/* mpllb cfg6 */
		0x0001,		/* mpllb cfg7 */
		0x6000,		/* mpllb cfg8 */
		0x0000,		/* mpllb cfg9 */
		0x0000,		/* mpllb cfg10 */
		},
};

static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
	.tx = {	0xbe88, /* tx cfg0 */
		0x4800, /* tx cfg1 */
		0x0000, /* tx cfg2 */
		},
	.cmn = {0x0500, /* cmn cfg0*/
		0x0005, /* cmn cfg1 */
		0x0000, /* cmn cfg2 */
		0x0000, /* cmn cfg3 */
		},
	.mpllb = { 0x308c,	/* mpllb cfg0 */

Annotation

Implementation Notes