drivers/gpu/drm/i915/display/intel_cx0_phy.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_cx0_phy.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/i915/display/intel_cx0_phy.h
Extension: .h
Size: 3707 bytes
Lines: 90
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/types.h

Detected Declarations

struct drm_printer
struct intel_atomic_state
struct intel_c10pll_state
struct intel_c20pll_state
struct intel_crtc
struct intel_crtc_state
struct intel_cx0pll_state
struct intel_display
struct intel_dpll
struct intel_dpll_hw_state
struct intel_encoder
struct intel_hdmi
enum icl_port_dpll_id

Annotated Snippet

#ifndef __INTEL_CX0_PHY_H__
#define __INTEL_CX0_PHY_H__

#include <linux/types.h>

#define MB_WRITE_COMMITTED      true
#define MB_WRITE_UNCOMMITTED    false

struct drm_printer;
enum icl_port_dpll_id;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_cx0pll_state;
struct intel_display;
struct intel_dpll;
struct intel_dpll_hw_state;
struct intel_encoder;
struct intel_hdmi;

void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
					 int lane);
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
			  struct intel_dpll *pll,
			  const struct intel_dpll_hw_state *dpll_hw_state);
void intel_mtl_pll_disable(struct intel_encoder *encoder);
enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
			const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
				const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder,
				    int port_clock);
void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder);

int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
			    struct intel_encoder *encoder,
			    struct intel_dpll_hw_state *hw_state);
bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
				   struct intel_cx0pll_state *pll_state);
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
				 const struct intel_cx0pll_state *pll_state);

void intel_cx0pll_dump_hw_state(struct drm_printer *p,
				const struct intel_cx0pll_state *hw_state);
bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
				   const struct intel_cx0pll_state *b);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
				     const struct intel_crtc_state *crtc_state);
void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
					 u8 lane_mask, u8 state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
bool intel_cx0_is_hdmi_frl(u32 clock);
u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr);
void intel_cx0_rmw(struct intel_encoder *encoder,
		   u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed);
void intel_cx0_write(struct intel_encoder *encoder,
		     u8 lane_mask, u16 addr, u8 data, bool committed);
int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
			   int command, int lane, u32 *val);
void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane);

void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state);
bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
					struct intel_dpll *pll,
					struct intel_dpll_hw_state *hw_state);
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);

void intel_cx0pll_verify_plls(struct intel_display *display);
void intel_cx0_pll_power_save_wa(struct intel_display *display);
void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
				 const struct intel_crtc_state *crtc_state);
void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
			      const struct intel_crtc_state *crtc_state);
void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder);

#endif /* __INTEL_CX0_PHY_H__ */

Annotation

Immediate include surface: `linux/types.h`.
Detected declarations: `struct drm_printer`, `struct intel_atomic_state`, `struct intel_c10pll_state`, `struct intel_c20pll_state`, `struct intel_crtc`, `struct intel_crtc_state`, `struct intel_cx0pll_state`, `struct intel_display`, `struct intel_dpll`, `struct intel_dpll_hw_state`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.