drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
Extension
.h
Size
20566 bytes
Lines
437
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INTEL_CX0_PHY_REGS_H__
#define __INTEL_CX0_PHY_REGS_H__

#include "intel_display_limits.h"
#include "intel_display_reg_defs.h"

/* DDI Buffer Control */
#define _DDI_CLK_VALFREQ_A		0x64030
#define _DDI_CLK_VALFREQ_B		0x64130
#define DDI_CLK_VALFREQ(port)		_MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)

/*
 * Wrapper macro to convert from port number to the index used in some of the
 * registers. For Display version 20 and above it converts the port number to a
 * single range, starting with the TC offsets. When used together with
 * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second
 * range. Example:
 *
 * PORT_TC1 -> PORT_TC1
 * PORT_TC2 -> PORT_TC2
 * PORT_TC3 -> PORT_TC3
 * PORT_TC4 -> PORT_TC4
 * PORT_A   -> PORT_TC4 + 1
 * PORT_B   -> PORT_TC4 + 2
 * ...
 */
#define __xe2lpd_port_idx(port)						\
	(port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)

#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A		0x64040
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B		0x64140
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1		0x16F240
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2		0x16F440
#define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane)				\
	(DISPLAY_VER(i915__) >= 20 ?						\
	 _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) :		\
	 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
#define   XELPDP_PORT_M2P_TRANSACTION_PENDING		REG_BIT(31)
#define   XELPDP_PORT_M2P_COMMAND_TYPE_MASK		REG_GENMASK(30, 27)
#define   XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED	REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
#define   XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED	REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
#define   XELPDP_PORT_M2P_COMMAND_READ			REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
#define   XELPDP_PORT_P2P_TRANSACTION_PENDING		REG_BIT(24)
#define   XELPDP_PORT_M2P_DATA_MASK			REG_GENMASK(23, 16)
#define   XELPDP_PORT_M2P_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
#define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
#define   XELPDP_PORT_M2P_ADDRESS_MASK			REG_GENMASK(11, 0)
#define   XELPDP_PORT_M2P_ADDRESS(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)

#define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane)			\
	(DISPLAY_VER(i915__) >= 20 ?						\
	 _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) :	\
	 _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
#define   XELPDP_PORT_P2M_RESPONSE_READY		REG_BIT(31)
#define   XELPDP_PORT_P2M_COMMAND_TYPE_MASK		REG_GENMASK(30, 27)
#define   XELPDP_PORT_P2M_COMMAND_READ_ACK		0x4
#define   XELPDP_PORT_P2M_COMMAND_WRITE_ACK		0x5
#define   XELPDP_PORT_P2M_DATA_MASK			REG_GENMASK(23, 16)
#define   XELPDP_PORT_P2M_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
#define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)

#define XELPDP_MSGBUS_TIMEOUT_MS			1
#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
#define XELPDP_PORT_RESET_START_TIMEOUT_US		10
#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS		2
#define XELPDP_PORT_RESET_END_TIMEOUT_MS		15
#define XELPDP_REFCLK_ENABLE_TIMEOUT_US			10

#define _XELPDP_PORT_BUF_CTL1_LN0_A			0x64004
#define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104
#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1			0x16F200
#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2			0x16F400
#define _XELPDP_PORT_BUF_CTL1(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
										 _XELPDP_PORT_BUF_CTL1_LN0_B, \
										 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
										 _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
#define XELPDP_PORT_BUF_CTL1(i915__, port)					\

Annotation

Implementation Notes