drivers/gpu/drm/i915/display/intel_ddi.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_ddi.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_ddi.c
Extension
.c
Size
169393 bytes
Lines
5517
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (clock) {
		case 162000:
			return DDI_CLK_SEL_TBT_162;
		case 270000:
			return DDI_CLK_SEL_TBT_270;
		case 540000:
			return DDI_CLK_SEL_TBT_540;
		case 810000:
			return DDI_CLK_SEL_TBT_810;
		default:
			MISSING_CASE(clock);
			return DDI_CLK_SEL_NONE;
		}
	case DPLL_ID_ICL_MGPLL1:
	case DPLL_ID_ICL_MGPLL2:
	case DPLL_ID_ICL_MGPLL3:
	case DPLL_ID_ICL_MGPLL4:
	case DPLL_ID_TGL_MGPLL5:
	case DPLL_ID_TGL_MGPLL6:
		return DDI_CLK_SEL_MG;
	}
}

static u32 ddi_buf_phy_link_rate(int port_clock)
{
	switch (port_clock) {
	case 162000:
		return DDI_BUF_PHY_LINK_RATE(0);
	case 216000:
		return DDI_BUF_PHY_LINK_RATE(4);
	case 243000:
		return DDI_BUF_PHY_LINK_RATE(5);
	case 270000:
		return DDI_BUF_PHY_LINK_RATE(1);
	case 324000:
		return DDI_BUF_PHY_LINK_RATE(6);
	case 432000:
		return DDI_BUF_PHY_LINK_RATE(7);
	case 540000:
		return DDI_BUF_PHY_LINK_RATE(2);
	case 810000:
		return DDI_BUF_PHY_LINK_RATE(3);
	default:
		MISSING_CASE(port_clock);
		return DDI_BUF_PHY_LINK_RATE(0);
	}
}

static int dp_phy_lane_stagger_delay(int port_clock)
{
	/*
	 * Return the number of symbol clocks delay used to stagger the
	 * assertion/desassertion of the port lane enables. The target delay
	 * time is 100 ns or greater, return the number of symbols specific to
	 * the provided port_clock (aka link clock) corresponding to this delay
	 * time, i.e. so that
	 *
	 * number_of_symbols * duration_of_one_symbol >= 100 ns
	 *
	 * The delay must be applied only on TypeC DP outputs, for everything else
	 * the delay must be set to 0.
	 *
	 * Return the number of link symbols per 100 ns:
	 * port_clock (10 kHz) -> bits    / 100 us
	 * / symbol_size       -> symbols / 100 us
	 * / 1000              -> symbols / 100 ns
	 */
	return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000);
}

static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
				      const struct intel_crtc_state *crtc_state)
{
	struct intel_display *display = to_intel_display(encoder);
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
	intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |
		DDI_BUF_TRANS_SELECT(0);

	if (dig_port->lane_reversal)
		intel_dp->DP |= DDI_BUF_PORT_REVERSAL;
	if (dig_port->ddi_a_4_lanes)
		intel_dp->DP |= DDI_A_4_LANES;

	if (DISPLAY_VER(display) >= 14) {
		if (intel_dp_is_uhbr(crtc_state))
			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
		else

Annotation

Implementation Notes