drivers/gpu/drm/i915/display/intel_display_clock_gating.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_display_clock_gating.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
Extension
.c
Size
7964 bytes
Lines
271
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright 2026 Intel Corporation
 */

#include <drm/intel/intel_gmd_misc_regs.h>

#include "intel_de.h"
#include "i9xx_plane_regs.h"
#include "intel_display.h"
#include "intel_display_clock_gating.h"
#include "intel_display_core.h"
#include "intel_display_regs.h"

static void intel_display_gen9_init_clock_gating(struct intel_display *display)
{
	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);

	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
	intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);

	/*
	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
	 * Display WA #0859: skl,bxt,kbl,glk,cfl
	 */
	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
}

void intel_display_skl_init_clock_gating(struct intel_display *display)
{
	/*
	 * WaCompressedResourceDisplayNewHashMode:skl,kbl
	 * Display WA #0390: skl,kbl
	 *
	 * Must match Sampler, Pixel Back End, and Media. See
	 * WaCompressedResourceSamplerPbeMediaNewHashMode.
	 */
	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);

	intel_display_gen9_init_clock_gating(display);

	/*
	 * WaFbcTurnOffFbcWatermark:skl
	 * Display WA #0562: skl
	 */
	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
}

void intel_display_kbl_init_clock_gating(struct intel_display *display)
{
	/*
	 * WaCompressedResourceDisplayNewHashMode:skl,kbl
	 * Display WA #0390: skl,kbl
	 *
	 * Must match Sampler, Pixel Back End, and Media. See
	 * WaCompressedResourceSamplerPbeMediaNewHashMode.
	 */
	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);

	intel_display_gen9_init_clock_gating(display);

	/*
	 * WaFbcTurnOffFbcWatermark:kbl
	 * Display WA #0562: kbl
	 */
	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
}

void intel_display_cfl_init_clock_gating(struct intel_display *display)
{
	/*
	 * WaCompressedResourceDisplayNewHashMode:skl,kbl (and cfl, cml)
	 * Display WA #0390: skl,kbl (and cfl, cml)
	 *
	 * Must match Sampler, Pixel Back End, and Media. See
	 * WaCompressedResourceSamplerPbeMediaNewHashMode.
	 *
	 * NOTE: this is the same workaround used for skl and kbl,
	 * because the original implementation was checking HAS_LLC(),
	 * which cfl/cml have, even though the comment for the
	 * workaround doesn't mention it.
	 *
	 */
	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);

	intel_display_gen9_init_clock_gating(display);

	/*
	 * WaFbcTurnOffFbcWatermark:cfl

Annotation

Implementation Notes