drivers/gpu/drm/i915/display/intel_display_device.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_display_device.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_display_device.h
Extension
.h
Size
13113 bytes
Lines
353
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct intel_display_platforms {
	union {
		struct {
			INTEL_DISPLAY_PLATFORMS(__MEMBER);
		};
		DECLARE_BITMAP(bitmap, __NUM_PLATFORMS);
	};
};

#undef __MEMBER
#undef __COUNT
#undef __NUM_PLATFORMS

#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
	/* Keep in alphabetical order */ \
	func(cursor_needs_physical); \
	func(has_cdclk_crawl); \
	func(has_cdclk_squash); \
	func(has_ddi); \
	func(has_dp_mst); \
	func(has_dsb); \
	func(has_fpga_dbg); \
	func(has_gmch); \
	func(has_hotplug); \
	func(has_hti); \
	func(has_ipc); \
	func(has_overlay); \
	func(has_psr); \
	func(has_psr_hw_tracking); \
	func(overlay_needs_physical); \
	func(supports_tv);

#define HAS_128B_Y_TILING(__display)	(!(__display)->platform.i915g && !(__display)->platform.i915gm)
#define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
#define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
#define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
#define HAS_AUX_DIST(__display)		(IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake)
#define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
#define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
#define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
#define HAS_CDCLK_SQUASH(__display)	(DISPLAY_INFO(__display)->has_cdclk_squash)
#define HAS_CMRR(__display)		(DISPLAY_VER(__display) >= 20)
#define HAS_CMTG(__display)		(!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
#define HAS_CUR_FBC(__display)		(!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
#define HAS_D12_PLANE_MINIMIZATION(__display)	((__display)->platform.rocketlake || (__display)->platform.alderlake_s)
#define HAS_DBUF_OVERLAP_DETECTION(__display)	(DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection)
#define HAS_DDI(__display)		(DISPLAY_INFO(__display)->has_ddi)
#define HAS_DISPLAY(__display)		(DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0)
#define HAS_DMC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dmc)
#define HAS_DOUBLE_BUFFERED_M_N(__display)	(IS_DISPLAY_VER((__display), 9, 14) || (__display)->platform.broadwell)
#define HAS_DOUBLE_BUFFERED_LUT(__display)	(DISPLAY_VER(__display) >= 30)
#define HAS_DOUBLE_WIDE(__display)	(DISPLAY_VER(__display) < 4)
#define HAS_DP20(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
#define HAS_DPT(__display)		(DISPLAY_VER(__display) >= 13)
#define HAS_DP_MST(__display)		(DISPLAY_INFO(__display)->has_dp_mst)
#define HAS_DSB(__display)		(DISPLAY_INFO(__display)->has_dsb)
#define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
#define HAS_DSC_3ENGINES(__display)	(DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
#define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
#define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
#define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
#define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
#define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
#define HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
#define HAS_GMBUS_IRQ(__display)	(DISPLAY_VER(__display) >= 4)
#define HAS_GMCH(__display)		(DISPLAY_INFO(__display)->has_gmch)
#define HAS_FDI(__display)		(IS_DISPLAY_VER((__display), 5, 8) && !HAS_GMCH(__display))
#define HAS_HOTPLUG(__display)		(DISPLAY_INFO(__display)->has_hotplug)
#define HAS_HW_SAGV_WM(__display)	(DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx)
#define HAS_IPC(__display)		(DISPLAY_INFO(__display)->has_ipc)
#define HAS_IPS(__display)		((__display)->platform.haswell_ult || (__display)->platform.broadwell)
#define HAS_LRR(__display)		(DISPLAY_VER(__display) >= 12)
#define HAS_LSPCON(__display)		(IS_DISPLAY_VER(__display, 9, 10))
#define HAS_LT_PHY(__display)		((__display)->platform.novalake)
#define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
#define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
#define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
#define HAS_PIPEDMC(__display)		(DISPLAY_VER(__display) >= 12)
#define HAS_PIXEL_NORMALIZER(__display)	(DISPLAY_VER(__display) >= 35)
#define HAS_PSR(__display)		(DISPLAY_INFO(__display)->has_psr)
#define HAS_PSR_HW_TRACKING(__display)	(DISPLAY_INFO(__display)->has_psr_hw_tracking)
#define HAS_PSR2_SEL_FETCH(__display)	(DISPLAY_VER(__display) >= 12)
#define HAS_PSR_TRANS_PUSH_FRAME_CHANGE(__display)	(DISPLAY_VER(__display) >= 20)
#define HAS_SAGV(__display)		(DISPLAY_VER(__display) >= 9 && \
					 !(__display)->platform.broxton && !(__display)->platform.geminilake)
#define HAS_SAGV_WM(__display)		(DISPLAY_VER(__display) >= 12 && !(__display)->platform.rocketlake)
#define HAS_TRANSCODER(__display, trans)	((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
						  BIT(trans)) != 0)
#define HAS_UNCOMPRESSED_JOINER(__display)	(DISPLAY_VER(__display) >= 13)

Annotation

Implementation Notes