drivers/gpu/drm/i915/display/intel_display_power_well.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_display_power_well.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_display_power_well.h
Extension
.h
Size
5925 bytes
Lines
180
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct i915_power_well_instance {
	const char *name;
	const struct i915_power_domain_list {
		const enum intel_display_power_domain *list;
		u8 count;
	} *domain_list;

	/* unique identifier for this power well */
	enum i915_power_well_id id;
	/*
	 * Arbitrary data associated with this power well. Platform and power
	 * well specific.
	 */
	union {
		struct {
			/*
			 * request/status flag index in the PUNIT power well
			 * control/status registers.
			 */
			u8 idx;
		} vlv;
		struct {
			enum dpio_phy phy;
		} bxt;
		struct {
			/*
			 * request/status flag index in the power well
			 * control/status registers.
			 */
			u8 idx;
		} hsw;
		struct {
			u8 aux_ch;
		} xelpdp;
	};
};

struct i915_power_well_desc {
	const struct i915_power_well_ops *ops;
	const struct i915_power_well_instance_list {
		const struct i915_power_well_instance *list;
		u8 count;
	} *instances;

	/* Mask of pipes whose IRQ logic is backed by the pw */
	u16 irq_pipe_mask:4;
	u16 always_on:1;
	/*
	 * Instead of waiting for the status bit to ack enables,
	 * just wait a specific amount of time and then consider
	 * the well enabled.
	 */
	u16 fixed_enable_delay:1;
	u16 has_fuses:1;
	/*
	 * The pw is for an ICL+ TypeC PHY port in
	 * Thunderbolt mode.
	 */
	u16 is_tc_tbt:1;
	/* Enable timeout if greater than the default 1ms */
	u16 enable_timeout;
};

struct i915_power_well {
	const struct i915_power_well_desc *desc;
	struct intel_power_domain_mask domains;
	/* power well enable/disable usage count */
	int count;
	/* cached hw enabled state */
	bool hw_enabled;
	/* index into desc->instances->list */
	u8 instance_idx;
};

struct i915_power_well *lookup_power_well(struct intel_display *display,
					  enum i915_power_well_id id);

void intel_power_well_enable(struct intel_display *display,
			     struct i915_power_well *power_well);
void intel_power_well_disable(struct intel_display *display,
			      struct i915_power_well *power_well);
void intel_power_well_sync_hw(struct intel_display *display,
			      struct i915_power_well *power_well);
void intel_power_well_get(struct intel_display *display,
			  struct i915_power_well *power_well);
void intel_power_well_put(struct intel_display *display,
			  struct i915_power_well *power_well);
bool intel_power_well_is_enabled(struct intel_display *display,
				 struct i915_power_well *power_well);
bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well);

Annotation

Implementation Notes