drivers/gpu/drm/i915/display/intel_display_wa.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_display_wa.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_display_wa.c
Extension
.c
Size
5495 bytes
Lines
163
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2023 Intel Corporation
 */

#include <drm/drm_print.h>
#include <drm/intel/step.h>

#include "intel_de.h"
#include "intel_display_core.h"
#include "intel_display_regs.h"
#include "intel_display_wa.h"

static void gen11_display_wa_apply(struct intel_display *display)
{
	/* Wa_14010594013 */
	intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
}

static void xe_d_display_wa_apply(struct intel_display *display)
{
	/* Wa_14013723622 */
	intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
}

static void adlp_display_wa_apply(struct intel_display *display)
{
	/* Wa_22011091694:adlp */
	intel_de_rmw(display, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);

	/* Bspec/49189 Initialize Sequence */
	intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
}

static void xe3plpd_display_wa_apply(struct intel_display *display)
{
	/* Wa_22021451799 */
	intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DMG_GATING_DIS);
}

void intel_display_wa_apply(struct intel_display *display)
{
	if (DISPLAY_VER(display) == 35)
		xe3plpd_display_wa_apply(display);
	else if (display->platform.alderlake_p)
		adlp_display_wa_apply(display);
	else if (DISPLAY_VER(display) == 12)
		xe_d_display_wa_apply(display);
	else if (DISPLAY_VER(display) == 11)
		gen11_display_wa_apply(display);
}

/*
 * Wa_16025573575:
 * Fixes: Issue with bitbashing on Xe3 based platforms.
 * Workaround: Set masks bits in GPIO CTL and preserve it during bitbashing sequence.
 */
static bool intel_display_needs_wa_16025573575(struct intel_display *display)
{
	return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 ||
		DISPLAY_VERx100(display) == 3500;
}

/*
 * Wa_14011503117:
 * Fixes: Before enabling the scaler DE fatal error is masked
 * Workaround: Unmask the DE fatal error register after enabling the scaler
 * and after waiting of at least 1 frame.
 */
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)
{
	switch (wa) {
	case INTEL_DISPLAY_WA_1409120013:
		return IS_DISPLAY_VER(display, 11, 12);
	case INTEL_DISPLAY_WA_1409767108:
		return (display->platform.alderlake_s ||
			(display->platform.rocketlake &&
			 IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)));
	case INTEL_DISPLAY_WA_13012396614:
		return DISPLAY_VERx100(display) == 3000 ||
			DISPLAY_VERx100(display) == 3500;
	case INTEL_DISPLAY_WA_14010477008:
		return display->platform.dg1 || display->platform.rocketlake ||
			(display->platform.tigerlake &&
			 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0));
	case INTEL_DISPLAY_WA_14010480278:
		return (IS_DISPLAY_VER(display, 10, 12));
	case INTEL_DISPLAY_WA_14010547955:
		return display->platform.dg2;
	case INTEL_DISPLAY_WA_14010685332:

Annotation

Implementation Notes