drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
Extension
.h
Size
7947 bytes
Lines
208
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct intel_dkl_phy_reg {
	u32 reg:24;
	u32 bank_idx:4;
};

#define _DKL_PHY1_BASE					0x168000
#define _DKL_PHY2_BASE					0x169000
#define _DKL_PHY3_BASE					0x16A000
#define _DKL_PHY4_BASE					0x16B000
#define _DKL_PHY5_BASE					0x16C000
#define _DKL_PHY6_BASE					0x16D000

#define DKL_REG_TC_PORT(__reg) \
	(TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))

/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
#define DKL_REG_MMIO(__reg)				_MMIO((__reg).reg)

#define _DKL_REG_PHY_BASE(tc_port)			_PORT(tc_port, \
							      _DKL_PHY1_BASE, \
							      _DKL_PHY2_BASE)

#define _DKL_BANK_SHIFT					12
#define _DKL_REG_BANK_OFFSET(phy_offset) \
	((phy_offset) & ((1 << _DKL_BANK_SHIFT) - 1))
#define _DKL_REG_BANK_IDX(phy_offset) \
	(((phy_offset) >> _DKL_BANK_SHIFT) & 0xf)

#define _DKL_REG(tc_port, phy_offset)	\
	((const struct intel_dkl_phy_reg) { \
		.reg = _DKL_REG_PHY_BASE(tc_port) + \
		       _DKL_REG_BANK_OFFSET(phy_offset), \
		.bank_idx = _DKL_REG_BANK_IDX(phy_offset), \
	})

#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \
	_DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))

#define _DKL_PCS_DW5_LN0				0x0014
#define _DKL_PCS_DW5_LN1				0x1014
#define DKL_PCS_DW5(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
								    _DKL_PCS_DW5_LN0, \
								    _DKL_PCS_DW5_LN1)
#define   DKL_PCS_DW5_CORE_SOFTRESET			REG_BIT(11)

#define _DKL_PLL_DIV0					0x2200
#define DKL_PLL_DIV0(tc_port)				_DKL_REG(tc_port, \
								 _DKL_PLL_DIV0)
#define   DKL_PLL_DIV0_AFC_STARTUP_MASK			REG_GENMASK(27, 25)
#define   DKL_PLL_DIV0_AFC_STARTUP(val)			REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
#define   DKL_PLL_DIV0_INTEG_COEFF(x)			((x) << 16)
#define   DKL_PLL_DIV0_INTEG_COEFF_MASK			(0x1F << 16)
#define   DKL_PLL_DIV0_PROP_COEFF(x)			((x) << 12)
#define   DKL_PLL_DIV0_PROP_COEFF_MASK			(0xF << 12)
#define   DKL_PLL_DIV0_FBPREDIV_SHIFT			(8)
#define   DKL_PLL_DIV0_FBPREDIV(x)			((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
#define   DKL_PLL_DIV0_FBPREDIV_MASK			(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
#define   DKL_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
#define   DKL_PLL_DIV0_FBDIV_INT_MASK			(0xFF << 0)
#define   DKL_PLL_DIV0_MASK				(DKL_PLL_DIV0_INTEG_COEFF_MASK | \
							 DKL_PLL_DIV0_PROP_COEFF_MASK | \
							 DKL_PLL_DIV0_FBPREDIV_MASK | \
							 DKL_PLL_DIV0_FBDIV_INT_MASK)

#define _DKL_PLL_DIV1					0x2204
#define DKL_PLL_DIV1(tc_port)				_DKL_REG(tc_port, \
								 _DKL_PLL_DIV1)
#define   DKL_PLL_DIV1_IREF_TRIM(x)			((x) << 16)
#define   DKL_PLL_DIV1_IREF_TRIM_MASK			(0x1F << 16)
#define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)		((x) << 0)
#define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK		(0xFF << 0)

#define _DKL_PLL_SSC					0x2210
#define DKL_PLL_SSC(tc_port)				_DKL_REG(tc_port, \
								 _DKL_PLL_SSC)
#define   DKL_PLL_SSC_IREF_NDIV_RATIO(x)		((x) << 29)
#define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK		(0x7 << 29)
#define   DKL_PLL_SSC_STEP_LEN(x)			((x) << 16)
#define   DKL_PLL_SSC_STEP_LEN_MASK			(0xFF << 16)
#define   DKL_PLL_SSC_STEP_NUM(x)			((x) << 11)
#define   DKL_PLL_SSC_STEP_NUM_MASK			(0x7 << 11)
#define   DKL_PLL_SSC_EN				(1 << 9)

#define _DKL_PLL_BIAS					0x2214
#define DKL_PLL_BIAS(tc_port)				_DKL_REG(tc_port, \
								 _DKL_PLL_BIAS)
#define   DKL_PLL_BIAS_FRAC_EN_H			(1 << 30)
#define   DKL_PLL_BIAS_FBDIV_SHIFT			(8)
#define   DKL_PLL_BIAS_FBDIV_FRAC(x)			((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
#define   DKL_PLL_BIAS_FBDIV_FRAC_MASK			(0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)

Annotation

Implementation Notes