drivers/gpu/drm/i915/display/intel_dmc_regs.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_dmc_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/display/intel_dmc_regs.h- Extension
.h- Size
- 25238 bytes
- Lines
- 648
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
intel_display_reg_defs.h
Detected Declarations
enum dmc_event_idenum maindmc_event_idenum pipedmc_event_id
Annotated Snippet
#ifndef __INTEL_DMC_REGS_H__
#define __INTEL_DMC_REGS_H__
#include "intel_display_reg_defs.h"
enum dmc_event_id {
DMC_EVENT_TRUE = 0x0,
DMC_EVENT_FALSE = 0x1,
};
enum maindmc_event_id {
MAINDMC_EVENT_CMP_ZERO = 0x8,
MAINDMC_EVENT_CMP_ODD = 0x9,
MAINDMC_EVENT_CMP_NEG = 0xa,
MAINDMC_EVENT_CMP_CARRY = 0xb,
MAINDMC_EVENT_TMR0_DONE = 0x14,
MAINDMC_EVENT_TMR1_DONE = 0x15,
MAINDMC_EVENT_TMR2_DONE = 0x16,
MAINDMC_EVENT_COUNT0_DONE = 0x17,
MAINDMC_EVENT_COUNT1_DONE = 0x18,
MAINDMC_EVENT_PERF_CNTR_DARBF = 0x19,
MAINDMC_EVENT_SCANLINE_INRANGE_FQ_A_TRIGGER = 0x22,
MAINDMC_EVENT_SCANLINE_INRANGE_FQ_B_TRIGGER = 0x23,
MAINDMC_EVENT_SCANLINE_INRANGE_FQ_C_TRIGGER = 0x24,
MAINDMC_EVENT_SCANLINE_INRANGE_FQ_D_TRIGGER = 0x25,
MAINDMC_EVENT_1KHZ_FQ_A_TRIGGER = 0x26,
MAINDMC_EVENT_1KHZ_FQ_B_TRIGGER = 0x27,
MAINDMC_EVENT_1KHZ_FQ_C_TRIGGER = 0x28,
MAINDMC_EVENT_1KHZ_FQ_D_TRIGGER = 0x29,
MAINDMC_EVENT_SCANLINE_COMP_A = 0x2a,
MAINDMC_EVENT_SCANLINE_COMP_B = 0x2b,
MAINDMC_EVENT_SCANLINE_COMP_C = 0x2c,
MAINDMC_EVENT_SCANLINE_COMP_D = 0x2d,
MAINDMC_EVENT_VBLANK_DELAYED_A = 0x2e,
MAINDMC_EVENT_VBLANK_DELAYED_B = 0x2f,
MAINDMC_EVENT_VBLANK_DELAYED_C = 0x30,
MAINDMC_EVENT_VBLANK_DELAYED_D = 0x31,
MAINDMC_EVENT_VBLANK_A = 0x32,
MAINDMC_EVENT_VBLANK_B = 0x33,
MAINDMC_EVENT_VBLANK_C = 0x34,
MAINDMC_EVENT_VBLANK_D = 0x35,
MAINDMC_EVENT_HBLANK_A = 0x36,
MAINDMC_EVENT_HBLANK_B = 0x37,
MAINDMC_EVENT_HBLANK_C = 0x38,
MAINDMC_EVENT_HBLANK_D = 0x39,
MAINDMC_EVENT_VSYNC_A = 0x3a,
MAINDMC_EVENT_VSYNC_B = 0x3b,
MAINDMC_EVENT_VSYNC_C = 0x3c,
MAINDMC_EVENT_VSYNC_D = 0x3d,
MAINDMC_EVENT_SCANLINE_A = 0x3e,
MAINDMC_EVENT_SCANLINE_B = 0x3f,
MAINDMC_EVENT_SCANLINE_C = 0x40,
MAINDMC_EVENT_SCANLINE_D = 0x41,
MAINDMC_EVENT_PLANE1_FLIP_A = 0x42,
MAINDMC_EVENT_PLANE2_FLIP_A = 0x43,
MAINDMC_EVENT_PLANE3_FLIP_A = 0x44,
MAINDMC_EVENT_PLANE4_FLIP_A = 0x45,
MAINDMC_EVENT_PLANE5_FLIP_A = 0x46,
MAINDMC_EVENT_PLANE6_FLIP_A = 0x47,
MAINDMC_EVENT_PLANE7_FLIP_A = 0x48,
MAINDMC_EVENT_PLANE1_FLIP_B = 0x49,
MAINDMC_EVENT_PLANE2_FLIP_B = 0x4a,
MAINDMC_EVENT_PLANE3_FLIP_B = 0x4b,
MAINDMC_EVENT_PLANE4_FLIP_B = 0x4c,
MAINDMC_EVENT_PLANE5_FLIP_B = 0x4d,
MAINDMC_EVENT_PLANE6_FLIP_B = 0x4e,
MAINDMC_EVENT_PLANE7_FLIP_B = 0x4f,
MAINDMC_EVENT_PLANE1_FLIP_C = 0x50,
MAINDMC_EVENT_PLANE2_FLIP_C = 0x51,
MAINDMC_EVENT_PLANE3_FLIP_C = 0x52,
MAINDMC_EVENT_PLANE4_FLIP_C = 0x53,
MAINDMC_EVENT_PLANE5_FLIP_C = 0x54,
MAINDMC_EVENT_PLANE6_FLIP_C = 0x55,
MAINDMC_EVENT_PLANE7_FLIP_C = 0x56,
MAINDMC_EVENT_PLANE1_FLIP_D = 0x57,
MAINDMC_EVENT_PLANE2_FLIP_D = 0x58,
MAINDMC_EVENT_PLANE3_FLIP_D = 0x59,
MAINDMC_EVENT_PLANE4_FLIP_D = 0x5a,
MAINDMC_EVENT_PLANE5_FLIP_D = 0x5b,
MAINDMC_EVENT_PLANE6_FLIP_D = 0x5c,
MAINDMC_EVENT_PLANE7_FLIP_D = 0x5d,
MAINDMC_EVENT_PLANE1_FLIP_DONE_A = 0x5e,
MAINDMC_EVENT_PLANE2_FLIP_DONE_A = 0x5f,
MAINDMC_EVENT_PLANE3_FLIP_DONE_A = 0x60,
MAINDMC_EVENT_PLANE4_FLIP_DONE_A = 0x61,
MAINDMC_EVENT_PLANE5_FLIP_DONE_A = 0x62,
MAINDMC_EVENT_PLANE6_FLIP_DONE_A = 0x63,
Annotation
- Immediate include surface: `intel_display_reg_defs.h`.
- Detected declarations: `enum dmc_event_id`, `enum maindmc_event_id`, `enum pipedmc_event_id`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.