drivers/gpu/drm/i915/display/intel_dmc_wl.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_dmc_wl.c

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/i915/display/intel_dmc_wl.c
Extension: .c
Size: 13584 bytes
Lines: 514
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/kernel.h
drm/drm_print.h
intel_de.h
intel_display_regs.h
intel_dmc_regs.h
intel_dmc_wl.h

Detected Declarations

struct intel_dmc_wl_range
function __intel_dmc_wl_release
function intel_dmc_wl_work
function __intel_dmc_wl_take
function intel_dmc_wl_reg_in_range
function intel_dmc_wl_check_range
function __intel_dmc_wl_supported
function intel_dmc_wl_sanitize_param
function intel_dmc_wl_init
function intel_dmc_wl_enable
function intel_dmc_wl_disable
function intel_dmc_wl_flush_release_work
function intel_dmc_wl_get
function intel_dmc_wl_put
function intel_dmc_wl_get_noreg
function intel_dmc_wl_put_noreg

Annotated Snippet

struct intel_dmc_wl_range {
	u32 start;
	u32 end;
};

static const struct intel_dmc_wl_range powered_off_ranges[] = {
	{ .start = 0x44400, .end = 0x4447f }, /* PIPE interrupt registers */
	{ .start = 0x60000, .end = 0x7ffff },
	{},
};

static const struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = {
	{ .start = 0x45500 }, /* DC_STATE_SEL */
	{ .start = 0x457a0, .end = 0x457b0 }, /* DC*_RESIDENCY_COUNTER */
	{ .start = 0x45504 }, /* DC_STATE_EN */
	{ .start = 0x45400, .end = 0x4540c }, /* PWR_WELL_CTL_* */
	{ .start = 0x454f0 }, /* RETENTION_CTRL */

	/* DBUF_CTL_* */
	{ .start = 0x44300 },
	{ .start = 0x44304 },
	{ .start = 0x44f00 },
	{ .start = 0x44f04 },
	{ .start = 0x44fe8 },
	{ .start = 0x45008 },

	{ .start = 0x46070 }, /* CDCLK_PLL_ENABLE */
	{ .start = 0x46000 }, /* CDCLK_CTL */
	{ .start = 0x46008 }, /* CDCLK_SQUASH_CTL */

	/* TRANS_CMTG_CTL_* */
	{ .start = 0x6fa88 },
	{ .start = 0x6fb88 },

	{ .start = 0x46430 }, /* CHICKEN_DCPR_1 */
	{ .start = 0x46434 }, /* CHICKEN_DCPR_2 */
	{ .start = 0x454a0 }, /* CHICKEN_DCPR_4 */
	{ .start = 0x42084 }, /* CHICKEN_MISC_2 */
	{ .start = 0x42088 }, /* CHICKEN_MISC_3 */
	{ .start = 0x46160 }, /* CMTG_CLK_SEL */
	{ .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */
	{ .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */

	{},
};

static const struct intel_dmc_wl_range xe3lpd_dc3co_dmc_ranges[] = {
	{ .start = 0x454a0 }, /* CHICKEN_DCPR_4 */

	{ .start = 0x45504 }, /* DC_STATE_EN */

	/* DBUF_CTL_* */
	{ .start = 0x44300 },
	{ .start = 0x44304 },
	{ .start = 0x44f00 },
	{ .start = 0x44f04 },
	{ .start = 0x44fe8 },
	{ .start = 0x45008 },

	{ .start = 0x46070 }, /* CDCLK_PLL_ENABLE */
	{ .start = 0x46000 }, /* CDCLK_CTL */
	{ .start = 0x46008 }, /* CDCLK_SQUASH_CTL */
	{ .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */

	/* Scanline registers */
	{ .start = 0x70000 },
	{ .start = 0x70004 },
	{ .start = 0x70014 },
	{ .start = 0x70018 },
	{ .start = 0x71000 },
	{ .start = 0x71004 },
	{ .start = 0x71014 },
	{ .start = 0x71018 },
	{ .start = 0x72000 },
	{ .start = 0x72004 },
	{ .start = 0x72014 },
	{ .start = 0x72018 },
	{ .start = 0x73000 },
	{ .start = 0x73004 },
	{ .start = 0x73014 },
	{ .start = 0x73018 },
	{ .start = 0x7b000 },
	{ .start = 0x7b004 },
	{ .start = 0x7b014 },
	{ .start = 0x7b018 },
	{ .start = 0x7c000 },
	{ .start = 0x7c004 },
	{ .start = 0x7c014 },
	{ .start = 0x7c018 },

Annotation

Immediate include surface: `linux/kernel.h`, `drm/drm_print.h`, `intel_de.h`, `intel_display_regs.h`, `intel_dmc_regs.h`, `intel_dmc_wl.h`.
Detected declarations: `struct intel_dmc_wl_range`, `function __intel_dmc_wl_release`, `function intel_dmc_wl_work`, `function __intel_dmc_wl_take`, `function intel_dmc_wl_reg_in_range`, `function intel_dmc_wl_check_range`, `function __intel_dmc_wl_supported`, `function intel_dmc_wl_sanitize_param`, `function intel_dmc_wl_init`, `function intel_dmc_wl_enable`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.