drivers/gpu/drm/i915/display/intel_dp_mst.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_dp_mst.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/display/intel_dp_mst.c- Extension
.c- Size
- 69751 bytes
- Lines
- 2193
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/log2.hlinux/math.hdrm/drm_atomic.hdrm/drm_atomic_helper.hdrm/drm_edid.hdrm/drm_fixed.hdrm/drm_print.hdrm/drm_probe_helper.hdrm/intel/step.hintel_atomic.hintel_audio.hintel_connector.hintel_crtc.hintel_ddi.hintel_de.hintel_display_driver.hintel_display_regs.hintel_display_types.hintel_display_utils.hintel_display_wa.hintel_dp.hintel_dp_hdcp.hintel_dp_link_training.hintel_dp_mst.hintel_dp_test.hintel_dp_tunnel.hintel_dpio_phy.hintel_hdcp.hintel_hotplug.hintel_link_bw.hintel_pfit.hintel_psr.h
Detected Declarations
function intel_dp_mst_active_streamsfunction intel_dp_mst_dec_active_streamsfunction intel_dp_mst_inc_active_streamsfunction intel_dp_mst_max_dpt_bppfunction intel_dp_mst_bw_overheadfunction intel_dp_mst_compute_m_nfunction intel_dp_mst_calc_pbnfunction intel_dp_mst_dsc_get_slice_countfunction mst_stream_update_slotsfunction intel_dp_mtp_tu_compute_configfunction mst_stream_compute_link_configfunction mst_stream_dsc_compute_link_configfunction mode_hblank_period_nsfunction hblank_expansion_quirk_needs_dscfunction adjust_limits_for_dsc_hblank_expansion_quirkfunction mst_stream_compute_config_limitsfunction mst_stream_compute_link_for_joined_pipesfunction mst_stream_compute_configfunction for_each_joiner_candidatefunction intel_dp_mst_transcoder_maskfunction for_each_new_intel_connector_in_statefunction get_pipes_downstream_of_mst_portfunction for_each_new_intel_connector_in_statefunction intel_dp_mst_check_dsc_changefunction for_each_intel_crtc_in_pipe_maskfunction intel_dp_mst_check_bwfunction intel_dp_mst_atomic_check_linkfunction for_each_new_mst_mgr_in_statefunction mst_stream_compute_config_latefunction intel_modeset_pipe_configfunction mst_connector_atomic_checkfunction mst_stream_disablefunction mst_stream_post_disablefunction for_each_pipe_crtc_modeset_disablefunction for_each_pipe_crtc_modeset_disablefunction mst_stream_post_pll_disablefunction mst_stream_pre_pll_enablefunction intel_mst_probed_link_params_validfunction intel_mst_set_probed_link_paramsfunction intel_mst_reprobe_topologyfunction mst_stream_pre_enablefunction enable_bs_jitter_wasfunction mst_stream_enablefunction for_each_pipe_crtc_modeset_enablefunction mst_stream_get_hw_statefunction mst_stream_get_configfunction mst_stream_initial_fastset_checkfunction mst_connector_get_ddc_modes
Annotated Snippet
if (!dsc_slice_count) {
drm_dbg_kms(display->drm, "Can't get valid DSC slice count\n");
return -ENOSPC;
}
}
drm_WARN_ON(display->drm, min_bpp_x16 % bpp_step_x16 || max_bpp_x16 % bpp_step_x16);
for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) {
int local_bw_overhead;
int link_bpp_x16;
drm_dbg_kms(display->drm, "Trying bpp " FXP_Q4_FMT "\n", FXP_Q4_ARGS(bpp_x16));
if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) {
/* SST must have validated the single bpp tried here already earlier. */
drm_WARN_ON(display->drm, !is_mst);
continue;
}
link_bpp_x16 = dsc ? bpp_x16 :
intel_dp_output_format_link_bpp_x16(crtc_state->output_format,
fxp_q4_to_int(bpp_x16));
local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
false, dsc_slice_count, link_bpp_x16);
intel_dp_mst_compute_m_n(crtc_state,
local_bw_overhead,
link_bpp_x16,
&crtc_state->dp_m_n);
if (is_mst) {
int remote_bw_overhead;
int remote_tu;
fixed20_12 pbn;
remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
true, dsc_slice_count, link_bpp_x16);
/*
* The TU size programmed to the HW determines which slots in
* an MTP frame are used for this stream, which needs to match
* the payload size programmed to the first downstream branch
* device's payload table.
*
* Note that atm the payload's PBN value DRM core sends via
* the ALLOCATE_PAYLOAD side-band message matches the payload
* size (which it calculates from the PBN value) it programs
* to the first branch device's payload table. The allocation
* in the payload table could be reduced though (to
* crtc_state->dp_m_n.tu), provided that the driver doesn't
* enable SSC on the corresponding link.
*/
pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
link_bpp_x16,
remote_bw_overhead));
remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);
/*
* Aligning the TUs ensures that symbols consisting of multiple
* (4) symbol cycles don't get split between two consecutive
* MTPs, as required by Bspec.
* TODO: remove the alignment restriction for 128b/132b links
* on some platforms, where Bspec allows this.
*/
remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
/*
* Also align PBNs accordingly, since MST core will derive its
* own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
* The above comment about the difference between the PBN
* allocated for the whole path and the TUs allocated for the
* first branch device's link also applies here.
*/
pbn.full = remote_tu * mst_state->pbn_div.full;
drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
crtc_state->dp_m_n.tu = remote_tu;
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst.mgr,
connector->mst.port,
dfixed_trunc(pbn));
/* TODO: Check this already in drm_dp_atomic_find_time_slots(). */
if (slots > mst_state->total_avail_slots)
slots = -EINVAL;
} else {
/* Same as above for remote_tu */
Annotation
- Immediate include surface: `linux/log2.h`, `linux/math.h`, `drm/drm_atomic.h`, `drm/drm_atomic_helper.h`, `drm/drm_edid.h`, `drm/drm_fixed.h`, `drm/drm_print.h`, `drm/drm_probe_helper.h`.
- Detected declarations: `function intel_dp_mst_active_streams`, `function intel_dp_mst_dec_active_streams`, `function intel_dp_mst_inc_active_streams`, `function intel_dp_mst_max_dpt_bpp`, `function intel_dp_mst_bw_overhead`, `function intel_dp_mst_compute_m_n`, `function intel_dp_mst_calc_pbn`, `function intel_dp_mst_dsc_get_slice_count`, `function mst_stream_update_slots`, `function intel_dp_mtp_tu_compute_config`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.