drivers/gpu/drm/i915/display/intel_dpll.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_dpll.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/display/intel_dpll.c- Extension
.c- Size
- 67642 bytes
- Lines
- 2320
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/string_helpers.hdrm/drm_print.hintel_atomic.hintel_crtc.hintel_cx0_phy.hintel_de.hintel_display.hintel_display_regs.hintel_display_types.hintel_dpio_phy.hintel_dpll.hintel_lt_phy.hintel_lvds.hintel_lvds_regs.hintel_panel.hintel_pps.hintel_snps_phy.hvlv_dpio_phy_regs.hvlv_sideband.h
Detected Declarations
struct intel_dpll_global_funcsstruct intel_limitfunction pnv_calc_dpll_paramsfunction i9xx_dpll_compute_mfunction i9xx_calc_dpll_paramsfunction vlv_calc_dpll_paramsfunction chv_calc_dpll_paramsfunction i9xx_pll_refclkfunction i9xx_dpll_get_hw_statefunction i9xx_crtc_clock_getfunction vlv_crtc_clock_getfunction chv_crtc_clock_getfunction intel_pll_is_validfunction i9xx_select_p2_divfunction i9xx_find_best_dpllfunction pnv_find_best_dpllfunction g4x_find_best_dpllfunction vlv_PLL_is_optimalfunction betterfunction vlv_find_best_dpllfunction chv_find_best_dpllfunction bxt_find_best_dpllfunction i9xx_dpll_compute_fpfunction pnv_dpll_compute_fpfunction i965_dpll_mdfunction i9xx_dpllfunction i9xx_compute_dpllfunction i8xx_dpllfunction i8xx_compute_dpllfunction hsw_crtc_compute_clockfunction hsw_crtc_get_dpllfunction dg2_crtc_compute_clockfunction ilk_fb_cb_factorfunction ilk_needs_fb_cb_tunefunction ilk_dpll_compute_fpfunction ilk_dpllfunction ilk_compute_dpllfunction ilk_crtc_compute_clockfunction ilk_crtc_get_dpllfunction vlv_dpllfunction vlv_compute_dpllfunction chv_dpllfunction chv_compute_dpllfunction chv_crtc_compute_clockfunction vlv_crtc_compute_clockfunction g4x_crtc_compute_clockfunction intel_crtc_has_typefunction pnv_crtc_compute_clock
Annotated Snippet
struct intel_dpll_global_funcs {
int (*crtc_compute_clock)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*crtc_get_dpll)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
};
struct intel_limit {
struct {
int min, max;
} dot, vco, n, m, m1, m2, p, p1;
struct {
int dot_limit;
int p2_slow, p2_fast;
} p2;
};
static const struct intel_limit intel_limits_i8xx_dac = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 },
.m = { .min = 96, .max = 140 },
.m1 = { .min = 18, .max = 26 },
.m2 = { .min = 6, .max = 16 },
.p = { .min = 4, .max = 128 },
.p1 = { .min = 2, .max = 33 },
.p2 = { .dot_limit = 165000,
.p2_slow = 4, .p2_fast = 2 },
};
static const struct intel_limit intel_limits_i8xx_dvo = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 },
.m = { .min = 96, .max = 140 },
.m1 = { .min = 18, .max = 26 },
.m2 = { .min = 6, .max = 16 },
.p = { .min = 4, .max = 128 },
.p1 = { .min = 2, .max = 33 },
.p2 = { .dot_limit = 165000,
.p2_slow = 4, .p2_fast = 4 },
};
static const struct intel_limit intel_limits_i8xx_lvds = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 },
.m = { .min = 96, .max = 140 },
.m1 = { .min = 18, .max = 26 },
.m2 = { .min = 6, .max = 16 },
.p = { .min = 4, .max = 128 },
.p1 = { .min = 1, .max = 6 },
.p2 = { .dot_limit = 165000,
.p2_slow = 14, .p2_fast = 7 },
};
static const struct intel_limit intel_limits_i9xx_sdvo = {
.dot = { .min = 20000, .max = 400000 },
.vco = { .min = 1400000, .max = 2800000 },
.n = { .min = 1, .max = 6 },
.m = { .min = 70, .max = 120 },
.m1 = { .min = 8, .max = 18 },
.m2 = { .min = 3, .max = 7 },
.p = { .min = 5, .max = 80 },
.p1 = { .min = 1, .max = 8 },
.p2 = { .dot_limit = 200000,
.p2_slow = 10, .p2_fast = 5 },
};
static const struct intel_limit intel_limits_i9xx_lvds = {
.dot = { .min = 20000, .max = 400000 },
.vco = { .min = 1400000, .max = 2800000 },
.n = { .min = 1, .max = 6 },
.m = { .min = 70, .max = 120 },
.m1 = { .min = 8, .max = 18 },
.m2 = { .min = 3, .max = 7 },
.p = { .min = 7, .max = 98 },
.p1 = { .min = 1, .max = 8 },
.p2 = { .dot_limit = 112000,
.p2_slow = 14, .p2_fast = 7 },
};
static const struct intel_limit intel_limits_g4x_sdvo = {
.dot = { .min = 25000, .max = 270000 },
.vco = { .min = 1750000, .max = 3500000},
.n = { .min = 1, .max = 4 },
.m = { .min = 104, .max = 138 },
.m1 = { .min = 17, .max = 23 },
.m2 = { .min = 5, .max = 11 },
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/string_helpers.h`, `drm/drm_print.h`, `intel_atomic.h`, `intel_crtc.h`, `intel_cx0_phy.h`, `intel_de.h`, `intel_display.h`.
- Detected declarations: `struct intel_dpll_global_funcs`, `struct intel_limit`, `function pnv_calc_dpll_params`, `function i9xx_dpll_compute_m`, `function i9xx_calc_dpll_params`, `function vlv_calc_dpll_params`, `function chv_calc_dpll_params`, `function i9xx_pll_refclk`, `function i9xx_dpll_get_hw_state`, `function i9xx_crtc_clock_get`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.